[main] added Cadence SYN and PaR scripts - initial version
[main] added Cadence SYN and PaR scripts - initial version
This commit is contained in:
ivanpiatak
216
scripts/scripts_PaR/RUN_PAR.tcl
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216
scripts/scripts_PaR/RUN_PAR.tcl
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### This is a sample RUN TCL file to control the stages of the digital ASIC BE flow
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### We are using RTL Compiler (synthesis) and Encounter (PaR) from the the Cadence Inc.
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### The current technology is XFAB 180nm
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### For current flow the following assumptions are expected:
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### - set all USER settings;
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### - check that netlist and exported synthesis SDC are exisits with consistent names;
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### - open the terminal
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### - cd to the main folder with the scripts, src, reports etc. (BE_ASIC_DESIGN_CADENCE_SCRIPTS folder)
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### - run Place-and-Route with Encounter by typing in the same terminal "Encounter ./RUN_PAR.tcl"
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### ================= USER SETTINGS =================
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set NETLIST_TOP_NAME "PWM_syn_netlist.v"; # RTL top module name
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set NETLIST_PATH "./results/results_syn"; # RTL path to the source files
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set PAR_SDC_TOP_NAME "PWM_syn.sdc"; # SDC top file name
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set PAR_SDC_PATH "./results/results_syn"; # SDC path to the sources
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set PAR_MMMC_FILE "./scripts/scripts_aux/XFAB180_typ.tcl"; # Multi-mode multi-corner file
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set PAR_NETLIST_TOP_PORT_FILE "./scripts/scripts_aux/PaR_NETLIST_TOP_PORT_FILE"; # Synthesis corner (typ by default)
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set PAR_INIT_LEF_FILESET "/Cadence/Libs/X_FAB/XKIT/xt018/cadence/v7_0/techLEF/v7_0_1_1/xt018_xx43_MET4_METMID_METTHK.lef \
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/Cadence/Libs/X_FAB/XKIT/xt018/diglibs/D_CELLS_HD/v4_0/LEF/v4_0_0/xt018_D_CELLS_HD.lef \
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/Cadence/Libs/X_FAB/XKIT/xt018/diglibs/D_CELLS_HD/v4_0/LEF/v4_0_0/xt018_xx43_MET4_METMID_METTHK_D_CELLS_HD_mprobe.lef";
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set PAR_REPORTS_FOLDER "./reports/reports_par"; # Reports folder
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set PAR_RESULTS_FOLDER "./results/results_par"; # Results folder
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set FLOORPLAN_DIMENSIONS "2000 2000"; # FP chip area
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set FLOORPLAN_MARGINS "50 50 50 50"; # FP chip margins
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### ================= END of USER SETTINGS =============
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### ================= INITIAL SETTINGS =================
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win
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set init_pwr_net VDD # Define supply VDD net
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set init_gnd_net VSS # Define supply VSS net
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set init_lef_file ${PAR_INIT_LEF_FILESET} # Physical libraries - LEF fileset from XFAB 180nm
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set init_design_settop 0
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set init_verilog ${NETLIST_PATH}/${NETLIST_TOP_NAME} # SYN netlist file
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set init_mmmc_file ${PAR_MMMC_FILE} # Techmological file for multi-mode multi-corner PaR
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set init_io_file ${PAR_NETLIST_TOP_PORT_FILE} # File with location of the TOP level ports on the floorplan
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init_design
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fit
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### ================= END of INITIAL SETTINGS =========
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### ================= FLOORPLANNING ====================
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floorPlan -site core_hd -s ${FLOORPLAN_DIMENSIONS} ${FLOORPLAN_MARGINS}
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floorPlan -coreMarginsBy die -site core_hd -s ${FLOORPLAN_DIMENSIONS} ${FLOORPLAN_MARGINS}
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fit
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### ================= END of FLOORPLANNING ============
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### ================= POWER DELIVERY SYSTEM ====================
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#GLOBAL CONNECTIONS
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clearGlobalNets
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globalNetConnect VDD -type pgpin -pin vdd -inst * -module {}
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globalNetConnect VSS -type pgpin -pin gnd -inst * -module {}
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globalNetConnect VDD -type tiehi -pin vdd -inst * -module {}
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globalNetConnect VSS -type tielo -pin gnd -inst * -module {}
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# POWER RING
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addRing -skip_via_on_wire_shape Noshape -skip_via_on_pin Standardcell -stacked_via_top_layer METTPL -type core_rings -jog_distance 3.15 -threshold 3.15 -nets {VDD VSS} -follow core -stacked_via_bottom_layer MET1 -layer {bottom MET1 top MET1 right MET2 left MET2} -width 15 -spacing 0.6 -offset 3.15
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# POWER STRAPS
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addStripe -skip_via_on_wire_shape Noshape -block_ring_top_layer_limit MET3 -max_same_layer_jog_length 6 -padcore_ring_bottom_layer_limit MET1 -set_to_set_distance 1000 -skip_via_on_pin Standardcell -stacked_via_top_layer METTPL -padcore_ring_top_layer_limit MET3 -spacing 5 -merge_stripes_value 3.15 -layer MET2 -block_ring_bottom_layer_limit MET1 -width 20 -nets {VSS VDD} -stacked_via_bottom_layer MET1
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# REMOVE UNUNSED
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selectWire 39.6900 6.5100 59.6900 5073.6900 2 VSS #TODO
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deleteSelectedFromFPlan #TODO
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selectWire 64.6900 22.1100 84.6900 5058.0900 2 VDD #TODO
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deleteSelectedFromFPlan #TODO
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# MAKE A PG CONNECTIONS
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sroute -connect { blockPin padPin padRing corePin floatingStripe } -layerChangeRange { MET1 METTPL } -blockPinTarget { nearestTarget } -padPinPortConnect { allPort oneGeom } -padPinTarget { nearestTarget } -corePinTarget { firstAfterRowEnd } -floatingStripeTarget { blockring padring ring stripe ringpin blockpin followpin } -allowJogging 1 -crossoverViaLayerRange { MET1 METTPL } -allowLayerChange 1 -nets { VDD VSS } -blockPin useLef -targetViaLayerRange { MET1 METTPL }
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editPowerVia -skip_via_on_pin Standardcell -bottom_layer MET1 -add_vias 1 -top_layer METTPL
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# AFTER-STAGE STA
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timeDesign -prePlace -idealClock -pathReports -drvReports -slackReports -numPaths 50 -prefix ${NETLIST_TOP_NAME}_FP_PG_SETUP -outDir ${PAR_REPORTS_FOLDER} # SETUP STA
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suspend
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### ================= END of POWER DELIVERY SYSTEM ============
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### ================= PLACEMENT ====================
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# GENERAL SETTINGS - CPU num etc.
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setMultiCpuUsage -localCpu 8 -cpuPerRemoteHost 1 -remoteHost 0 -keepLicense true
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setDistributeHost -local
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setPlaceMode -fp false
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### PLACE
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placeDesign -inPlaceOpt
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# POST-PLACE STA
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timeDesign -preCTS -idealClock -pathReports -drvReports -slackReports -numPaths 50 -prefix ${NETLIST_TOP_NAME}_PLACE_SETUP -outDir ${PAR_REPORTS_FOLDER} # SETUP STA
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timeDesign -preCTS -hold -idealClock -pathReports -slackReports -numPaths 50 -prefix ${NETLIST_TOP_NAME}_PLACE_HOLD -outDir ${PAR_REPORTS_FOLDER} # HOLD STA
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suspend
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# OPTIMIZATION
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setOptMode -fixCap true -fixTran true -fixFanoutLoad true
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optDesign -preCTS
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# POST-OPTIMIZATION STA
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timeDesign -preCTS -hold -idealClock -pathReports -slackReports -numPaths 50 -prefix ${NETLIST_TOP_NAME}_PLACE_HOLD_OPT -outDir ${PAR_REPORTS_FOLDER} # HOLD STA
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suspend
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### ================= END of PLACEMENT =============
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### ================= CTS ====================
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# BUFFER SORTING
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createClockTreeSpec -bufferList {BUHDX0 BUHDX1 BUHDX12 BUHDX2 BUHDX3 BUHDX4 BUHDX6 BUHDX8 DLY1HDX0 DLY1HDX1 DLY2HDX0 DLY2HDX1 DLY4HDX0 DLY4HDX1 DLY8HDX0 DLY8HDX1 INHDX0 INHDX1 INHDX12 INHDX2 INHDX3 INHDX4 INHDX6 INHDX8 STEHDX0 STEHDX1 STEHDX2 STEHDX4} -file Clock.ctstch
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# CTS
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setCTSMode -engine ck
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clockDesign -specFile Clock.ctstch -outDir ${PAR_REPORTS_FOLDER} -fixedInstBeforeCTS
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# POST-CTS STA
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timeDesign -postCTS -pathReports -drvReports -slackReports -numPaths 50 -prefix ${NETLIST_TOP_NAME}_CTS_SETUP -outDir ${PAR_REPORTS_FOLDER} # SETUP STA
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timeDesign -postCTS -hold -pathReports -slackReports -numPaths 50 -prefix ${NETLIST_TOP_NAME}_CTS_HOLD -outDir ${PAR_REPORTS_FOLDER} # HOLD STA
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suspend
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### OPTIMIZATION
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setOptMode -fixCap true -fixTran true -fixFanoutLoad true
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optDesign -postCTS
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optDesign -postCTS -hold
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# POST-OPT STA
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timeDesign -postCTS -hold -pathReports -slackReports -numPaths 50 -prefix ${NETLIST_TOP_NAME}_CTS_HOLD_OPT -outDir ${PAR_REPORTS_FOLDER} # HOLD STA
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suspend
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# INCREMENTAL OPT
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optDesign -postCTS -hold -incr
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# POST-INCR STA
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timeDesign -postCTS -hold -pathReports -slackReports -numPaths 50 -prefix ${NETLIST_TOP_NAME}_CTS_HOLD_INCR_OPT -outDir ${PAR_REPORTS_FOLDER} # HOLD STA
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suspend
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### ================= END of CTS =============
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### ================= ROUTE ====================
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# GENERAL SETTINGS
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setNanoRouteMode -quiet -timingEngine {}
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setNanoRouteMode -quiet -routeWithSiPostRouteFix 0
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setNanoRouteMode -quiet -routeTopRoutingLayer default
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setNanoRouteMode -quiet -routeBottomRoutingLayer default
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setNanoRouteMode -quiet -drouteEndIteration default
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setNanoRouteMode -quiet -routeWithTimingDriven false
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setNanoRouteMode -quiet -routeWithSiDriven false
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# ANTENNA VILOATION FIX - BRIDGE
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setNanoRouteMode -quiet -drouteFixAntenna true
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# ANTENNA VILOATION FIX - DIODES
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setNanoRouteMode -quiet -routeInsertAntennaDiode true
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# ROUTE
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routeDesign -globalDetail
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# POST-ROUTE STA
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setAnalysisMode -analysisType onChipVariation -skew true -clockPropagation sdcControl
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timeDesign -postRoute -pathReports -drvReports -slackReports -numPaths 50 -prefix ${NETLIST_TOP_NAME}_ROUTE_SETUP -outDir ${PAR_REPORTS_FOLDER} # SETUP STA
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timeDesign -postRoute -hold -pathReports -slackReports -numPaths 50 -prefix ${NETLIST_TOP_NAME}_ROUTE_HOLD -outDir ${PAR_REPORTS_FOLDER} # HOLD STA
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suspend
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# OPTIMIZATION
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setOptMode -fixCap true -fixTran true -fixFanoutLoad true
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optDesign -postRoute
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optDesign -postRoute -hold
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# POST-OPT STA
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timeDesign -postRoute -hold -pathReports -slackReports -numPaths 50 -prefix ${NETLIST_TOP_NAME}_ROUTE_HOLD_OPT -outDir ${PAR_REPORTS_FOLDER} # HOLD STA
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suspend
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# INCREMENTAL OPT
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optDesign -postRoute -incr
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optDesign -postRoute -hold -incr
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# POST-INCR STA
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timeDesign -postRoute -hold -pathReports -slackReports -numPaths 50 -prefix ${NETLIST_TOP_NAME}_ROUTE_HOLD_INCR_OPT -outDir ${PAR_REPORTS_FOLDER} # HOLD STA
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suspend
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### ================= END of ROUTE ====================
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### ================= FINALIZATION ====================
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# FILLER CELLS
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getFillerMode -quiet
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addFiller -cell FEED7HD FEED5HD FEED3HD FEED2HD FEED25HD FEED1HD FEED15HD FEED10HD -prefix FILLER
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suspend
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# CHECK SIMPLE DRC
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setVerifyGeometryMode -area { 0 0 0 0 } -minWidth true -minSpacing true -minArea true -sameNet true -short true -overlap true -offRGrid false -offMGrid true -mergedMGridCheck true -minHole true -implantCheck true -minimumCut true -minStep true -viaEnclosure true -antenna false -insuffMetalOverlap true -pinInBlkg true -diffCellViol false -sameCellViol true -padFillerCellsOverlap false -routingBlkgPinOverlap false -routingCellBlkgOverlap false -regRoutingOnly false -stackedViasOnRegNet false -wireExt true -useNonDefaultSpacing false -maxWidth true -maxNonPrefLength -1 -error 1000
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verifyGeometry
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setVerifyGeometryMode -area { 0 0 0 0 }
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verify_drc -report ${PAR_REPORTS_FOLDER}/${NETLIST_TOP_NAME}_DRC.rpt -limit 1000
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verifyConnectivity -type all -error 1000 -warning 50
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# EXTRACT RC
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setExtractRCMode -engine postRoute -effortLevel signoff
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extractRC
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### ================= END of FINALIZATION ====================
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### ================= OUTPUT ====================
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# STA
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timeDesign -signoff -pathReports -drvReports -slackReports -numPaths 50 -prefix ${NETLIST_TOP_NAME}_SIGNOFF_SETUP -outDir ${PAR_REPORTS_FOLDER} # "-signoff" SETUP STA
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timeDesign -signoff -hold -pathReports -slackReports -numPaths 50 -prefix ${NETLIST_TOP_NAME}_SIGNOFF_HOLD -outDir ${PAR_REPORTS_FOLDER} # "-signoff" HOLD STA
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all_hold_analysis_views
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all_setup_analysis_views
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# EXPORT RESULTS of the PaR stage
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write_sdf -view TYPview ${PAR_RESULTS_FOLDER}/${NETLIST_TOP_NAME}.sdf
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saveNetlist ${PAR_RESULTS_FOLDER} -includePhysicalCell {FEED7HD FEED10HD FEED15HD FEED1HD FEED25HD FEED2HD FEED3HD FEED5HD}
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defOut -floorplan -netlist -routing ${PAR_RESULTS_FOLDER}/${NETLIST_TOP_NAME}.def
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### ================= END of OUTPUT ====================
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10001
scripts/scripts_aux/PaR_NETLIST_TOP_PORT_FILE
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10001
scripts/scripts_aux/PaR_NETLIST_TOP_PORT_FILE
Normal file
File diff suppressed because it is too large
Load Diff
87
scripts/scripts_aux/XFAB180_MMMC.tcl
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87
scripts/scripts_aux/XFAB180_MMMC.tcl
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@@ -0,0 +1,87 @@
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### Technology: "X-FAB 180 nm CMOS, XT018 1243"
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### Library: "D_CELLS_HD, 1.8V"
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### Tools: "Cadence Encounter"
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###
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### Stage: "PaR"
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### File description: "Multi-mode multi-corner (MMMC) file for the Cadence Encounter EDA tool"
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## Timing constraints file from the synthesis
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create_constraint_mode -name CONSTRAINTS -sdc_files {../Source/Constraints_synth_typ.sdc}
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## Create timing libraries sets
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# The slowest corner
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create_library_set -name SLOWlib \
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-timing {/Cadence/Libs/X_FAB/XKIT/xt018/diglibs/D_CELLS_HD/v4_0/liberty_LP5MOS/v4_0_0/PVT_1_80V_range/D_CELLS_HD_LP5MOS_slow_1_62V_175C.lib}
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# Typical corner
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create_library_set -name TYPlib \
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-timing {/Cadence/Libs/X_FAB/XKIT/xt018/diglibs/D_CELLS_HD/v4_0/liberty_LP5MOS/v4_0_0/PVT_1_80V_range/D_CELLS_HD_LP5MOS_typ_1_80V_25C.lib}
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# The fastest corner
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create_library_set -name FASTlib \
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-timing {/Cadence/Libs/X_FAB/XKIT/xt018/diglibs/D_CELLS_HD/v4_0/liberty_LP5MOS/v4_0_0/PVT_1_80V_range/D_CELLS_HD_LP5MOS_fast_1_98V_m40C.lib}
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## Create operating conditions (P-V-T) for the timing libraries (CAN BE ABSENT IF CONDITIONS ARE GENERAL)
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# The slowest operation condition
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create_op_cond -name PVT_slow_1_62V_175C \
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-library_file {/Cadence/Libs/X_FAB/XKIT/xt018/diglibs/D_CELLS_HD/v4_0/liberty_LP5MOS/v4_0_0/PVT_1_80V_range/D_CELLS_HD_LP5MOS_slow_1_62V_175C.lib} \
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-P {1} -V {1.62} -T {175}
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# Typical operation condition
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create_op_cond -name PVT_typ_1_80V_25C \
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-library_file {/Cadence/Libs/X_FAB/XKIT/xt018/diglibs/D_CELLS_HD/v4_0/liberty_LP5MOS/v4_0_0/PVT_1_80V_range/D_CELLS_HD_LP5MOS_typ_1_80V_25C.lib} \
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-P {1} -V {1.8} -T {25}
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# The fastest operation condition
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create_op_cond -name PVT_fast_1_98V_-40C \
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-library_file {/Cadence/Libs/X_FAB/XKIT/xt018/diglibs/D_CELLS_HD/v4_0/liberty_LP5MOS/v4_0_0/PVT_1_80V_range/D_CELLS_HD_LP5MOS_fast_1_98V_m40C.lib} \
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-P {1} -V {1.98} -T {-40}
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## Create RC corner(s) from capacitance table(s)
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create_rc_corner -name RCcornerMIN \
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-cap_table /Cadence/Libs/X_FAB/XKIT/xt018/cadence/v7_0/capTbl/v7_0_1/xt018_xx43_MET4_METMID_METTHK_min.capTbl \
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-qx_tech_file /Cadence/Libs/X_FAB/XKIT/xt018/cadence/v7_0/QRC_pvs/v7_0_3/XT018_1243/QRC-Min/qrcTechFile
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create_rc_corner -name RCcornerTYP \
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-cap_table /Cadence/Libs/X_FAB/XKIT/xt018/cadence/v7_0/capTbl/v7_0_1/xt018_xx43_MET4_METMID_METTHK_typ.capTbl \
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-qx_tech_file /Cadence/Libs/X_FAB/XKIT/xt018/cadence/v7_0/QRC_pvs/v7_0_3/XT018_1243/QRC-Typ/qrcTechFile
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create_rc_corner -name RCcornerMAX \
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-cap_table /Cadence/Libs/X_FAB/XKIT/xt018/cadence/v7_0/capTbl/v7_0_1/xt018_xx43_MET4_METMID_METTHK_max.capTbl \
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-qx_tech_file /Cadence/Libs/X_FAB/XKIT/xt018/cadence/v7_0/QRC_pvs/v7_0_3/XT018_1243/QRC-Max/qrcTechFile
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## Create delay corner(s)
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create_delay_corner -name DELAYcornerSLOW \
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-library_set SLOWlib \
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-rc_corner RCcornerMAX
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create_delay_corner -name DELAYcornerTYP \
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-library_set TYPlib \
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-rc_corner RCcornerTYP
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create_delay_corner -name DELAYcornerFAST \
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-library_set FASTlib \
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-rc_corner RCcornerMIN
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## Create analysis views
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create_analysis_view -name MAXview \
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-delay_corner {DELAYcornerSLOW} \
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-constraint_mode {CONSTRAINTS}
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create_analysis_view -name TYPview \
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-delay_corner {DELAYcornerTYP} \
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-constraint_mode {CONSTRAINTS}
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create_analysis_view -name MINview \
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-delay_corner {DELAYcornerFAST} \
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-constraint_mode {CONSTRAINTS}
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## Set analysis view to above for both setup and hold
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set_analysis_view -setup {TYPview} -hold {TYPview}
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26
scripts/scripts_aux/XFAB180_fast.tcl
Normal file
26
scripts/scripts_aux/XFAB180_fast.tcl
Normal file
@@ -0,0 +1,26 @@
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### Technology: "X-FAB 180 nm CMOS, XT018 1243"
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### Library: "D_CELLS_HD, 1.8V"
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### Tools: "Cadence RTL Compiler"
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###
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### Stage: "Synthesis"
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### File description: "Contains paths to the library of digital cells (slow corner)"
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# Setup path for liberty CPF directory
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set_attribute lib_search_path /Cadence/Libs/X_FAB/XKIT/xt018/diglibs/D_CELLS_HD/v4_0/liberty_LP5MOS/v4_0_0/PVT_1_80V_range
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||||
|
||||
# Setup PVT corner .lib file
|
||||
set_attribute library {/Cadence/Libs/X_FAB/XKIT/xt018/diglibs/D_CELLS_HD/v4_0/liberty_LP5MOS/v4_0_0/PVT_1_80V_range/D_CELLS_HD_LP5MOS_fast_1_98V_m40C.lib}
|
||||
|
||||
# Setup LEF files
|
||||
set_attribute lef_library { \
|
||||
/Cadence/Libs/X_FAB/XKIT/xt018/cadence/v7_0/techLEF/v7_0_1_1/xt018_xx43_MET4_METMID_METTHK.lef \
|
||||
/Cadence/Libs/X_FAB/XKIT/xt018/diglibs/D_CELLS_HD/v4_0/LEF/v4_0_0/xt018_D_CELLS_HD.lef \
|
||||
/Cadence/Libs/X_FAB/XKIT/xt018/diglibs/D_CELLS_HD/v4_0/LEF/v4_0_0/xt018_xx43_MET4_METMID_METTHK_D_CELLS_HD_mprobe.lef \
|
||||
}
|
||||
|
||||
# Setup capacitance table file
|
||||
set_attribute cap_table_file /Cadence/Libs/X_FAB/XKIT/xt018/cadence/v7_0/capTbl/v7_0_1/xt018_xx43_MET4_METMID_METTHK_fast.capTbl
|
||||
|
||||
# Setup error on blackbox
|
||||
set_attribute hdl_error_on_blackbox true
|
||||
26
scripts/scripts_aux/XFAB180_slow.tcl
Normal file
26
scripts/scripts_aux/XFAB180_slow.tcl
Normal file
@@ -0,0 +1,26 @@
|
||||
### Technology: "X-FAB 180 nm CMOS, XT018 1243"
|
||||
### Library: "D_CELLS_HD, 1.8V"
|
||||
### Tools: "Cadence RTL Compiler"
|
||||
###
|
||||
### Stage: "Synthesis"
|
||||
### File description: "Contains paths to the library of digital cells (slow corner)"
|
||||
|
||||
|
||||
# Setup path for liberty CPF directory
|
||||
set_attribute lib_search_path /Cadence/Libs/X_FAB/XKIT/xt018/diglibs/D_CELLS_HD/v4_0/liberty_LP5MOS/v4_0_0/PVT_1_80V_range
|
||||
|
||||
# Setup PVT corner .lib file
|
||||
set_attribute library {/Cadence/Libs/X_FAB/XKIT/xt018/diglibs/D_CELLS_HD/v4_0/liberty_LP5MOS/v4_0_0/PVT_1_80V_range/D_CELLS_HD_LP5MOS_slow_1_62V_175C.lib}
|
||||
|
||||
# Setup LEF files
|
||||
set_attribute lef_library { \
|
||||
/Cadence/Libs/X_FAB/XKIT/xt018/cadence/v7_0/techLEF/v7_0_1_1/xt018_xx43_MET4_METMID_METTHK.lef \
|
||||
/Cadence/Libs/X_FAB/XKIT/xt018/diglibs/D_CELLS_HD/v4_0/LEF/v4_0_0/xt018_D_CELLS_HD.lef \
|
||||
/Cadence/Libs/X_FAB/XKIT/xt018/diglibs/D_CELLS_HD/v4_0/LEF/v4_0_0/xt018_xx43_MET4_METMID_METTHK_D_CELLS_HD_mprobe.lef \
|
||||
}
|
||||
|
||||
# Setup capacitance table file
|
||||
set_attribute cap_table_file /Cadence/Libs/X_FAB/XKIT/xt018/cadence/v7_0/capTbl/v7_0_1/xt018_xx43_MET4_METMID_METTHK_slow.capTbl
|
||||
|
||||
# Setup error on blackbox
|
||||
set_attribute hdl_error_on_blackbox true
|
||||
26
scripts/scripts_aux/XFAB180_typ.tcl
Normal file
26
scripts/scripts_aux/XFAB180_typ.tcl
Normal file
@@ -0,0 +1,26 @@
|
||||
### Technology: "X-FAB 180 nm CMOS, XT018 1243"
|
||||
### Library: "D_CELLS_HD, 1.8V"
|
||||
### Tools: "Cadence RTL Compiler"
|
||||
###
|
||||
### Stage: "Synthesis"
|
||||
### File description: "Contains paths to the library of digital cells (slow corner)"
|
||||
|
||||
|
||||
# Setup path for liberty CPF directory
|
||||
set_attribute lib_search_path /Cadence/Libs/X_FAB/XKIT/xt018/diglibs/D_CELLS_HD/v4_0/liberty_LP5MOS/v4_0_0/PVT_1_80V_range
|
||||
|
||||
# Setup PVT corner .lib file
|
||||
set_attribute library {/Cadence/Libs/X_FAB/XKIT/xt018/diglibs/D_CELLS_HD/v4_0/liberty_LP5MOS/v4_0_0/PVT_1_80V_range/D_CELLS_HD_LP5MOS_typ_1_80V_25C.lib}
|
||||
|
||||
# Setup LEF files
|
||||
set_attribute lef_library { \
|
||||
/Cadence/Libs/X_FAB/XKIT/xt018/cadence/v7_0/techLEF/v7_0_1_1/xt018_xx43_MET4_METMID_METTHK.lef \
|
||||
/Cadence/Libs/X_FAB/XKIT/xt018/diglibs/D_CELLS_HD/v4_0/LEF/v4_0_0/xt018_D_CELLS_HD.lef \
|
||||
/Cadence/Libs/X_FAB/XKIT/xt018/diglibs/D_CELLS_HD/v4_0/LEF/v4_0_0/xt018_xx43_MET4_METMID_METTHK_D_CELLS_HD_mprobe.lef \
|
||||
}
|
||||
|
||||
# Setup capacitance table file
|
||||
set_attribute cap_table_file /Cadence/Libs/X_FAB/XKIT/xt018/cadence/v7_0/capTbl/v7_0_1/xt018_xx43_MET4_METMID_METTHK_typ.capTbl
|
||||
|
||||
# Setup error on blackbox
|
||||
set_attribute hdl_error_on_blackbox true
|
||||
61
scripts/scripts_syn/RUN_SYN.tcl
Normal file
61
scripts/scripts_syn/RUN_SYN.tcl
Normal file
@@ -0,0 +1,61 @@
|
||||
### This is a sample RUN TCL file to control the stages of the digital ASIC BE flow
|
||||
### We are using RTL Compiler (synthesis) and Encounter (PaR) from the the Cadence Inc.
|
||||
### The current technology is XFAB 180nm
|
||||
|
||||
### For current flow the following assumptions are expected:
|
||||
### - set all USER settings;
|
||||
### - create requred SDC file with the same name as your RTL top (e.g. RTL_TOP_MODULE.sdc)
|
||||
### - open the terminal
|
||||
### - cd to the main folder with the scripts, src, reports etc. (BE_ASIC_DESIGN_CADENCE_SCRIPTS folder)
|
||||
### - run synthesis with RTL Compiler by typing in the same terminal "RTL_Compiler ./RUN_SYN.tcl"
|
||||
|
||||
|
||||
|
||||
### ================= USER SETTINGS =================
|
||||
set RTL_TOP_NAME "PWM"; # RTL top module name
|
||||
set RTL_PATH "./src/rtl"; # RTL path to the source files
|
||||
|
||||
set RTL_FILELIST_NAME "filelist.v"; # RTL path to the filelist for synthesis
|
||||
|
||||
set SYN_SDC_TOP_NAME "${RTL_TOP_NAME}.sdc"; # SDC top file name
|
||||
set SYN_SDC_PATH "./src/sdc"; # SDC path to the sources
|
||||
|
||||
set SYN_CORNER "./scripts/scripts_aux/XFAB180_typ.tcl"; # Synthesis corner (typ by default)
|
||||
|
||||
set SYN_REPORTS_FOLDER "./reports/reports_syn"; # Reports folder
|
||||
set SYN_RESULTS_FOLDER "./results/results_syn"; # Results folder
|
||||
### ================= END of USER SETTINGS ==========
|
||||
|
||||
|
||||
|
||||
### ================= SYNTHESIS =================
|
||||
# Source desired corner technology file for synthesis
|
||||
include ${SYN_CORNER}
|
||||
|
||||
# Read in Verilog HDL filelist for synthesis
|
||||
read_hdl -v2001 ${RTL_PATH}/${RTL_FILELIST_NAME}
|
||||
|
||||
# Synthesize (elabirate, no mapping)
|
||||
elaborate ${RTL_TOP_NAME}
|
||||
|
||||
# Rear SDC constraints
|
||||
read_sdc ${SYN_SDC_PATH}/${SYN_SDC_TOP_NAME}
|
||||
|
||||
# Synthesize (technology mapped)
|
||||
synthesize -to_mapped
|
||||
synthesize -incremental
|
||||
|
||||
# Generate area and timing reports
|
||||
report timing > ${SYN_REPORTS_FOLDER}/${RTL_TOP_NAME}_syn_timing_report.rpt
|
||||
report area > ${SYN_REPORTS_FOLDER}/${RTL_TOP_NAME}_syn_area_report.rpt
|
||||
|
||||
# Export synthesized and mapped Verilog netlist - result of the synthesis
|
||||
write_hdl -mapped > ${SYN_RESULTS_FOLDER}/${RTL_TOP_NAME}_syn_netlist.v
|
||||
|
||||
# Export SDC file for the next PaR stages
|
||||
write_sdc > ${SYN_RESULTS_FOLDER}/${RTL_TOP_NAME}_syn.sdc
|
||||
|
||||
# Open RTL Compiler GUI
|
||||
gui_show
|
||||
|
||||
### ================= END of SYNTHESIS ==========
|
||||
46
src/rtl/PWM.v
Normal file
46
src/rtl/PWM.v
Normal file
@@ -0,0 +1,46 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 14:15:19 05/19/2018
|
||||
// Design Name:
|
||||
// Module Name: PWM
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
module PWM(clk, reset, LED);
|
||||
input clk, reset;
|
||||
output LED;
|
||||
|
||||
reg [26:0] cnt;
|
||||
reg [3:0] pwm_cnt;
|
||||
|
||||
//Input counter
|
||||
always @(posedge clk)
|
||||
if (reset)
|
||||
cnt <= 27'd0;
|
||||
else
|
||||
cnt<=cnt+27'd1;
|
||||
|
||||
wire [3:0] pwm_inp = cnt[26] ? ~cnt[25:22]: cnt[25:22];
|
||||
|
||||
//PWM comparator
|
||||
always @(posedge clk)
|
||||
if (reset)
|
||||
pwm_cnt <= 4'd0;
|
||||
else
|
||||
pwm_cnt <= pwm_cnt + 4'd1;
|
||||
|
||||
assign LED = (pwm_cnt<pwm_inp);
|
||||
|
||||
endmodule
|
||||
1
src/rtl/filelist.v
Normal file
1
src/rtl/filelist.v
Normal file
@@ -0,0 +1 @@
|
||||
`include "PWM.v"
|
||||
50
src/sdc/PWM.sdc
Normal file
50
src/sdc/PWM.sdc
Normal file
@@ -0,0 +1,50 @@
|
||||
### Stage: "Synthesis and PaR"
|
||||
### File description: "Constraints for the design"
|
||||
|
||||
|
||||
# SET LIB UNITS
|
||||
set_units -time 1.0ns;
|
||||
set_units -capacitance 1.0pF;
|
||||
|
||||
set_max_capacitance 0.5 [all_outputs]
|
||||
|
||||
### ====================== CLOCKS ===========================
|
||||
# CLOCK and UNCERTAINTY
|
||||
set CLK_NAME "clk";
|
||||
set CLK_PERIOD 40.0;
|
||||
set CLK_UNCERT 0.2;
|
||||
|
||||
# CLK WAIVEFORM RISE-FALL TIMES
|
||||
set MINRISE 0.20
|
||||
set MAXRISE 0.25
|
||||
set MINFALL 0.20
|
||||
set MAXFALL 0.25
|
||||
|
||||
# IO DELAYS
|
||||
set INPUT_DELAY_CLK [expr $CLK_PERIOD/2.0]
|
||||
set OUTPUT_DELAY_CLK [expr $CLK_PERIOD/2.0]
|
||||
|
||||
|
||||
|
||||
create_clock -name $CLK_NAME -period $CLK_PERIOD -waveform "0 [expr $CLK_PERIOD/2]" [get_ports CLK_NAME]
|
||||
set_clock_uncertainty $CLK_UNCERT [get_clocks $CLK_NAME]
|
||||
|
||||
set_clock_transition -rise -min $MINRISE [get_clocks $CLK_NAME]
|
||||
set_clock_transition -rise -max $MAXRISE [get_clocks $CLK_NAME]
|
||||
set_clock_transition -fall -min $MINFALL [get_clocks $CLK_NAME]
|
||||
set_clock_transition -fall -max $MAXFALL [get_clocks $CLK_NAME]
|
||||
|
||||
|
||||
|
||||
#set_input_delay -clock "clk" -max $INPUT_DELAY_CLK [all_inputs]
|
||||
#set_input_delay -clock "clk" -min $INPUT_DELAY_CLK [all_inputs]
|
||||
|
||||
set_output_delay -clock "clk" -max $OUTPUT_DELAY_CLK [all_outputs]
|
||||
set_output_delay -clock "clk" -min $OUTPUT_DELAY_CLK [all_outputs]
|
||||
|
||||
|
||||
|
||||
### ====================== RESETS ===========================
|
||||
set RST_NAME "reset"
|
||||
set_ideal_network [get_ports $RST_NAME]
|
||||
set_false_path -from [get_ports $RST_NAME]
|
||||
Reference in New Issue
Block a user