51 lines
1.4 KiB
Tcl
51 lines
1.4 KiB
Tcl
### Stage: "Synthesis and PaR"
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### File description: "Constraints for the design"
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# SET LIB UNITS
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set_units -time 1.0ns;
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set_units -capacitance 1.0pF;
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set_max_capacitance 0.5 [all_outputs]
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### ====================== CLOCKS ===========================
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# CLOCK and UNCERTAINTY
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set CLK_NAME "clk";
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set CLK_PERIOD 40.0;
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set CLK_UNCERT 0.2;
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# CLK WAIVEFORM RISE-FALL TIMES
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set MINRISE 0.20
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set MAXRISE 0.25
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set MINFALL 0.20
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set MAXFALL 0.25
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# IO DELAYS
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set INPUT_DELAY_CLK [expr $CLK_PERIOD/2.0]
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set OUTPUT_DELAY_CLK [expr $CLK_PERIOD/2.0]
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create_clock -name $CLK_NAME -period $CLK_PERIOD -waveform "0 [expr $CLK_PERIOD/2]" [get_ports CLK_NAME]
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set_clock_uncertainty $CLK_UNCERT [get_clocks $CLK_NAME]
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set_clock_transition -rise -min $MINRISE [get_clocks $CLK_NAME]
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set_clock_transition -rise -max $MAXRISE [get_clocks $CLK_NAME]
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set_clock_transition -fall -min $MINFALL [get_clocks $CLK_NAME]
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set_clock_transition -fall -max $MAXFALL [get_clocks $CLK_NAME]
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#set_input_delay -clock "clk" -max $INPUT_DELAY_CLK [all_inputs]
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#set_input_delay -clock "clk" -min $INPUT_DELAY_CLK [all_inputs]
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set_output_delay -clock "clk" -max $OUTPUT_DELAY_CLK [all_outputs]
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set_output_delay -clock "clk" -min $OUTPUT_DELAY_CLK [all_outputs]
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### ====================== RESETS ===========================
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set RST_NAME "reset"
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set_ideal_network [get_ports $RST_NAME]
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set_false_path -from [get_ports $RST_NAME]
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