Update RUN_PAR.tcl

scripts/scripts_PaR/FLOW_PAR.tcl

@@ -13,7 +13,7 @@ if {$PaR_INIT eq "TRUE"} {
 
    set init_verilog ${NETLIST_PATH}/${NETLIST_TOP_NAME};          # SYN netlist file
    set init_mmmc_file ${PAR_MMMC_FILE};                           # Techmological file for multi-mode multi-corner PaR
-   set init_io_file ${PAR_NETLIST_TOP_PORT_FILE};                 # File with location of the TOP level ports on the floorplan
+   #set init_io_file ${PAR_NETLIST_TOP_PORT_FILE};                 # File with location of the TOP level ports on the floorplan
  
    init_design
 }

scripts/scripts_PaR/RUN_PAR.tcl

@@ -12,10 +12,10 @@
 
 
 ### ================= USER SETTINGS =================
-set NETLIST_TOP_NAME "scr1_top_ahb_syn_netlist.v";                       # RTL top module name
+set NETLIST_TOP_NAME "scr1_core_top_syn_netlist.v";                       # RTL top module name
 set NETLIST_PATH "../results/results_syn";                       # RTL path to the source files
 
-set PAR_SDC_TOP_NAME "scr1_top_ahb_syn.sdc";                             # SDC top file name
+set PAR_SDC_TOP_NAME "scr1_core_top_syn.sdc";                             # SDC top file name
 set PAR_SDC_PATH "../results/results_syn";                       # SDC path to the sources
 
 set PAR_MMMC_FILE "../scripts/scripts_aux/XFAB180_MMMC.tcl";                        # Multi-mode multi-corner file
@@ -28,7 +28,7 @@ set PAR_INIT_LEF_FILESET "/Cadence/Libs/X_FAB/XKIT/xt018/cadence/v7_0/techLEF/v7
 set PAR_REPORTS_FOLDER "../reports/reports_PaR";                 # Reports folder
 set PAR_RESULTS_FOLDER "../results/results_PaR";                 # Results folder
 
-set FLOORPLAN_DIMENSIONS {9000 9000};    # FP chip area
+set FLOORPLAN_DIMENSIONS {500 500};    # FP chip area
 set FLOORPLAN_MARGINS    {50 50 50 50};  #FP chip margins
 ### ================= END of USER SETTINGS =============
 

scripts/scripts_syn/RUN_SYN.tcl

@@ -48,6 +48,9 @@ if {$MAPPING eq "TRUE"} {
    # Rear SDC constraints
    read_sdc ${SYN_SDC_PATH}/${SYN_SDC_TOP_NAME}
 
+   # For testing correctness of SDC uncomment the command below
+   #exit
+
    # Synthesize (technology mapped)
    synthesize -to_mapped
    synthesize -incremental

src/sdc/scr1_core_top.sdc

@@ -1,5 +1,5 @@
 ### Stage:				"Synthesis and PaR"
-### File description:			"Constraints for the design"
+### File description:	"Constraints for the design"
 
 
 # SET LIB UNITS
@@ -9,58 +9,57 @@ set_units -capacitance 1.0pF;
 set_max_capacitance 0.5 [all_outputs]
 
 ### ====================== CLOCKS ===========================
-#clock uncertainty: 200ps for all clocks
+# Clock period: 10 ns (100 MHz)
+set CLK_PERIOD 100
+
+
+# Clock uncertainty: 200 ps for all clocks
 set CLK_UNCERT 0.2;
-#transition: 1ns R/F
-
-# CLOCK PERIOD
-set CLK_PERIOD 11.13
-set TCK_PERIOD 100
-set RTC_CLK_PERIOD 10000
-
-# IO DELAYS
-set INPUT_DELAY_CLK       [expr $CLK_PERIOD/4.0]
-set OUTPUT_DELAY_CLK      [expr $CLK_PERIOD/4.0]
-
-set INPUT_DELAY_TCK       [expr $TCK_PERIOD/4.0]
-set OUTPUT_DELAY_TCK      [expr $TCK_PERIOD/4.0]
-
-#clk->100MHz 
-create_clock -name "clk" -period $CLK_PERIOD -waveform "0 [expr $CLK_PERIOD/2.0]" [get_ports "clk"]
 
 
+# Clock transition: 1 ns R/F
 set MINRISE 0
 set MAXRISE 1.0
 set MINFALL 0
 set MAXFALL 1.0
 
+
 # Clock setup
+create_clock -name "clk" -period $CLK_PERIOD -waveform "0 [expr $CLK_PERIOD/2.0]" [get_ports "clk"]
+
 set_clock_uncertainty $CLK_UNCERT [get_clocks "clk"]
+
 set_clock_transition -rise -min $MINRISE [get_clocks "clk"]
 set_clock_transition -rise -max $MAXRISE [get_clocks "clk"]
 set_clock_transition -fall -min $MINFALL [get_clocks "clk"]
 set_clock_transition -fall -max $MAXFALL [get_clocks "clk"]
 
+### ====================== DELAYS ===========================
+# IO delays: 2.5 ns
+set INPUT_DELAY_CLK       [expr $CLK_PERIOD/4.0]
+set OUTPUT_DELAY_CLK      [expr $CLK_PERIOD/4.0]
+
+
+# IO delays setup
+set_input_delay -clock "clk" -max $INPUT_DELAY_CLK [all_inputs]
+set_input_delay -clock "clk" -min $INPUT_DELAY_CLK [all_inputs]
+
+set_output_delay -clock "clk" -max $OUTPUT_DELAY_CLK [all_outputs]
+set_output_delay -clock "clk" -min $OUTPUT_DELAY_CLK [all_outputs]
+
+
 # Ideal networks
 set_ideal_network [get_ports "pwrup_rst_n"]
 set_ideal_network [get_ports "rst_n"]
 set_ideal_network [get_ports "cpu_rst_n"]
 set_ideal_network [get_ports "test_rst_n"]
-#set_ideal_network [get_ports "trst_n"]
+
 
 # False paths
 set_false_path -from [get_ports "pwrup_rst_n"]
 set_false_path -from [get_ports "rst_n"]
 set_false_path -from [get_ports "cpu_rst_n"]
 set_false_path -from [get_ports "test_rst_n"]
-#set_false_path -from [get_ports "trst_n"]
-
-#IO delays:
-set_input_delay -clock "clk" -max $INPUT_DELAY_CLK [all_inputs]
-set_input_delay -clock "clk" -min $INPUT_DELAY_CLK [all_inputs]
-
-set_output_delay -clock "clk" -max $OUTPUT_DELAY_CLK [all_outputs]
-set_output_delay -clock "clk" -min $OUTPUT_DELAY_CLK [all_outputs]
 
 
 set_case_analysis 0 [get_ports "test_mode"]     
@@ -77,7 +76,3 @@ set_case_analysis 0 [get_ports "test_mode"]
 #  |              |
 #  |--------------|
 
-
-
-
-