74 lines
2.9 KiB
Tcl
74 lines
2.9 KiB
Tcl
### This is a sample RUN TCL file to control the stages of the digital ASIC BE flow
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### We are using RTL Compiler (synthesis) and Encounter (PaR) from the the Cadence Inc.
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### The current technology is XFAB 180nm
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### For current flow the following assumptions are expected:
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### - set all USER settings;
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### - create requred SDC file with the same name as your RTL top (e.g. RTL_TOP_MODULE.sdc)
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### - open the terminal
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### - cd to the main folder with the scripts, src, reports etc. (BE_ASIC_DESIGN_CADENCE_SCRIPTS folder) and then cd to the ./WORK_TMP_FOLDER
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### - run synthesis with RTL Compiler by typing in the same terminal "RTL_Compiler ../scripts/scripts_syn/RUN_SYN.tcl"
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### ================= USER SETTINGS =================
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set RTL_TOP_NAME "scr1_core_top"; # RTL top module name
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set RTL_PATH "../src/rtl"; # RTL path to the source files
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set RTL_FILELIST_NAME "filelist.v"; # RTL path to the filelist for synthesis
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set SYN_SDC_TOP_NAME "${RTL_TOP_NAME}.sdc"; # SDC top file name
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set SYN_SDC_PATH "../src/sdc"; # SDC path to the sources
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set SYN_CORNER "../scripts/scripts_aux/XFAB180_typ.tcl"; # Synthesis corner (typ by default)
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set SYN_REPORTS_FOLDER "../reports/reports_syn"; # Reports folder
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set SYN_RESULTS_FOLDER "../results/results_syn"; # Results folder
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### ================= END of USER SETTINGS ==========
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### ============== PROC to run synthesis ============
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### Set TRUE to enable technological mapping and results export; otherwise only elaboration is active
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#set MAPPING "FALSE";
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set MAPPING "TRUE";
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### ========== end of PROC to run synthesis =========
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### ================= SYNTHESIS =================
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# Source desired corner technology file for synthesis
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include ${SYN_CORNER}
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# Read in Verilog HDL filelist for synthesis
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read_hdl -sv ${RTL_PATH}/${RTL_FILELIST_NAME}
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# Synthesize (elaborate, no mapping)
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elaborate ${RTL_TOP_NAME}
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if {$MAPPING eq "TRUE"} {
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# Rear SDC constraints
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read_sdc ${SYN_SDC_PATH}/${SYN_SDC_TOP_NAME}
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# For testing correctness of SDC uncomment the command below
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#exit
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# Synthesize (technology mapped)
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synthesize -to_mapped
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synthesize -incremental
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# Generate area and timing reports
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report timing > ${SYN_REPORTS_FOLDER}/${RTL_TOP_NAME}_syn_timing_report.rpt
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report area > ${SYN_REPORTS_FOLDER}/${RTL_TOP_NAME}_syn_area_report.rpt
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report_timing -lint -verbose > ${SYN_REPORTS_FOLDER}/${RTL_TOP_NAME}_syn_timing_problems.rpt
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# Export synthesized and mapped Verilog netlist - result of the synthesis
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write_hdl -mapped > ${SYN_RESULTS_FOLDER}/${RTL_TOP_NAME}_syn_netlist.v
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# Export SDC file for the next PaR stages
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write_sdc > ${SYN_RESULTS_FOLDER}/${RTL_TOP_NAME}_syn.sdc
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}
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# Open RTL Compiler GUI
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gui_show
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### ================= END of SYNTHESIS ==========
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