riscv_school/riscv_school_scr1
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Update scr1_core_top.sdc

Browse Source
This commit is contained in:
Mikhail Yenuchenko
2026-01-21 15:09:42 +03:00
parent da358566a4
commit 9ed2c9a8f4
1 changed files with 26 additions and 31 deletions
Download Patch File Download Diff File Expand all files Collapse all files

57
src/sdc/scr1_core_top.sdc
View File

@@ -1,5 +1,5 @@
### Stage: "Synthesis and PaR"
### File description: "Constraints for the design"
### File description: "Constraints for the design"
# SET LIB UNITS
@@ -9,58 +9,57 @@ set_units -capacitance 1.0pF;
set_max_capacitance 0.5 [all_outputs]
### ====================== CLOCKS ===========================
#clock uncertainty: 200ps for all clocks
# Clock period: 10 ns (100 MHz)
set CLK_PERIOD 100
# Clock uncertainty: 200 ps for all clocks
set CLK_UNCERT 0.2;
#transition: 1ns R/F
# CLOCK PERIOD
set CLK_PERIOD 11.13
set TCK_PERIOD 100
set RTC_CLK_PERIOD 10000
# IO DELAYS
set INPUT_DELAY_CLK [expr $CLK_PERIOD/4.0]
set OUTPUT_DELAY_CLK [expr $CLK_PERIOD/4.0]
set INPUT_DELAY_TCK [expr $TCK_PERIOD/4.0]
set OUTPUT_DELAY_TCK [expr $TCK_PERIOD/4.0]
#clk->100MHz
create_clock -name "clk" -period $CLK_PERIOD -waveform "0 [expr $CLK_PERIOD/2.0]" [get_ports "clk"]
# Clock transition: 1 ns R/F
set MINRISE 0
set MAXRISE 1.0
set MINFALL 0
set MAXFALL 1.0
# Clock setup
create_clock -name "clk" -period $CLK_PERIOD -waveform "0 [expr $CLK_PERIOD/2.0]" [get_ports "clk"]
set_clock_uncertainty $CLK_UNCERT [get_clocks "clk"]
set_clock_transition -rise -min $MINRISE [get_clocks "clk"]
set_clock_transition -rise -max $MAXRISE [get_clocks "clk"]
set_clock_transition -fall -min $MINFALL [get_clocks "clk"]
set_clock_transition -fall -max $MAXFALL [get_clocks "clk"]
### ====================== DELAYS ===========================
# IO delays: 2.5 ns
set INPUT_DELAY_CLK [expr $CLK_PERIOD/4.0]
set OUTPUT_DELAY_CLK [expr $CLK_PERIOD/4.0]
# IO delays setup
set_input_delay -clock "clk" -max $INPUT_DELAY_CLK [all_inputs]
set_input_delay -clock "clk" -min $INPUT_DELAY_CLK [all_inputs]
set_output_delay -clock "clk" -max $OUTPUT_DELAY_CLK [all_outputs]
set_output_delay -clock "clk" -min $OUTPUT_DELAY_CLK [all_outputs]
# Ideal networks
set_ideal_network [get_ports "pwrup_rst_n"]
set_ideal_network [get_ports "rst_n"]
set_ideal_network [get_ports "cpu_rst_n"]
set_ideal_network [get_ports "test_rst_n"]
#set_ideal_network [get_ports "trst_n"]
# False paths
set_false_path -from [get_ports "pwrup_rst_n"]
set_false_path -from [get_ports "rst_n"]
set_false_path -from [get_ports "cpu_rst_n"]
set_false_path -from [get_ports "test_rst_n"]
#set_false_path -from [get_ports "trst_n"]
#IO delays:
set_input_delay -clock "clk" -max $INPUT_DELAY_CLK [all_inputs]
set_input_delay -clock "clk" -min $INPUT_DELAY_CLK [all_inputs]
set_output_delay -clock "clk" -max $OUTPUT_DELAY_CLK [all_outputs]
set_output_delay -clock "clk" -min $OUTPUT_DELAY_CLK [all_outputs]
set_case_analysis 0 [get_ports "test_mode"]
@@ -77,7 +76,3 @@ set_case_analysis 0 [get_ports "test_mode"]
# | |
# |--------------|