139 lines
3.2 KiB
Makefile
139 lines
3.2 KiB
Makefile
# src_dir := $(dir $(lastword $(MAKEFILE_LIST)))
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rtl_src_dir := $(root_dir)/src/
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rtl_core_files ?= core.files
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rtl_top_files ?= ahb_top.files
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rtl_tb_files ?= ahb_tb.files
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rtl_inc_dir ?= $(root_dir)/src/includes
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rtl_inc_tb_dir ?= $(root_dir)/src/tb
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top_module ?= scr1_top_tb_ahb
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rtl_core_list := $(addprefix $(rtl_src_dir),$(shell cat $(rtl_src_dir)$(rtl_core_files)))
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rtl_top_list := $(addprefix $(rtl_src_dir),$(shell cat $(rtl_src_dir)$(rtl_top_files)))
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rtl_tb_list := $(addprefix $(rtl_src_dir),$(shell cat $(rtl_src_dir)$(rtl_tb_files)))
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sv_list := $(rtl_core_list) $(rtl_top_list) $(rtl_tb_list)
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ifeq ($(MAKECMDGOALS), $(filter $(MAKECMDGOALS),build_verilator build_verilator_wf))
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ifeq ($(BUS),AHB)
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export scr1_wrapper := $(root_dir)/sim/verilator_wrap/scr1_ahb_wrapper.c
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endif
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ifeq ($(BUS),AXI)
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export scr1_wrapper := $(root_dir)/sim/verilator_wrap/scr1_axi_wrapper.c
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endif
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export verilator_ver ?= $(shell expr `verilator --version | cut -f2 -d' '`)
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export verilator_ver_5x ?= $(shell expr `verilator --version | cut -f2 -d' '` \>= 5)
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ifeq "$(verilator_ver_5x)" "1"
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VERILATOR_5X_OPTS ?= --no-timing # conservative way
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endif
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endif
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.PHONY: build_modelsim build_vcs build_ncsim build_verilator build_verilator_wf
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default: build_modelsim
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build_modelsim: $(sv_list)
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cd $(bld_dir); \
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vlib work; \
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vmap work work; \
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vlog -work work -O1 -mfcu -sv \
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+incdir+$(rtl_inc_dir) \
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+incdir+$(rtl_inc_tb_dir) \
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+nowarnSVCHK \
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+define+SCR1_TRGT_SIMULATION \
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+define+$(SIM_TRACE_DEF) \
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+define+$(SIM_CFG_DEF) \
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$(SIM_BUILD_OPTS) \
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$(sv_list)
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build_vcs: $(sv_list)
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cd $(bld_dir); \
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vcs \
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-full64 \
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-lca \
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-sverilog \
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-notice \
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+lint=all,noVCDE,noNS,noVNGS,noSVA-DIU,noSVA-CE,noSVA-NSVU \
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-timescale=1ns/1ps \
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+incdir+$(rtl_inc_dir) \
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+incdir+$(rtl_inc_tb_dir) \
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+define+SCR1_TRGT_SIMULATION \
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+define+$(SIM_TRACE_DEF) \
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+define+$(SIM_CFG_DEF) \
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-nc \
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-debug_all \
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$(SIM_BUILD_OPTS) \
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$(sv_list)
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build_ncsim: $(sv_list)
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cd $(bld_dir); \
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irun \
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-elaborate \
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-64bit \
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-disable_sem2009 \
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-verbose \
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-timescale 1ns/1ps \
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-incdir $(rtl_inc_dir) \
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-incdir $(rtl_inc_tb_dir) \
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-debug \
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+define+SCR1_TRGT_SIMULATION \
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+define+$(SIM_TRACE_DEF) \
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+define+$(SIM_CFG_DEF) \
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$(SIM_BUILD_OPTS) \
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$(sv_list) \
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-top $(top_module)
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build_verilator: $(sv_list)
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cd $(bld_dir); \
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verilator \
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-cc \
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-sv \
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+1800-2017ext+sv \
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-Wno-fatal \
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$(VERILATOR_5X_OPTS) \
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--top-module $(top_module) \
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-DSCR1_TRGT_SIMULATION \
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-D$(SIM_TRACE_DEF) \
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-D$(SIM_CFG_DEF) \
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--clk clk \
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--exe $(scr1_wrapper) \
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--Mdir $(bld_dir)/verilator \
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-I$(rtl_inc_dir) \
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-I$(rtl_inc_tb_dir) \
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$(SIM_BUILD_OPTS) \
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$(sv_list); \
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cd verilator; \
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$(MAKE) -f V$(top_module).mk;
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build_verilator_wf: $(sv_list)
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cd $(bld_dir); \
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verilator \
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-cc \
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-sv \
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+1800-2017ext+sv \
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-Wno-fatal \
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$(VERILATOR_5X_OPTS) \
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--top-module $(top_module) \
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-DSCR1_TRGT_SIMULATION \
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-D$(SIM_TRACE_DEF) \
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-D$(SIM_CFG_DEF) \
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-CFLAGS -DVCD_TRACE -CFLAGS -DTRACE_LVLV=20 \
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-CFLAGS -DVCD_FNAME=simx.vcd \
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--clk clk \
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--exe $(scr1_wrapper) \
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--trace \
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--trace-params \
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--trace-structs \
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--trace-underscore \
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--Mdir $(bld_dir)/verilator \
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-I$(rtl_inc_dir) \
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-I$(rtl_inc_tb_dir) \
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$(SIM_BUILD_OPTS) \
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$(sv_list); \
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cd verilator; \
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$(MAKE) -f V$(top_module).mk;
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