Folder rename

2026-01-20 17:48:32 +03:00
parent 306061a76d
commit 23e0e58f8b
57 changed files with 37 additions and 37 deletions
--- a/src_ref/ahb_tb.files
+++ b/src_ref/ahb_tb.files
--- a/src_ref/ahb_top.files
+++ b/src_ref/ahb_top.files
--- a/src_ref/axi_tb.files
+++ b/src_ref/axi_tb.files
--- a/src_ref/axi_top.files
+++ b/src_ref/axi_top.files
--- a/src_ref/core.files
+++ b/src_ref/core.files
--- a/src_ref/core/pipeline/scr1_ipic.sv
+++ b/src_ref/core/pipeline/scr1_ipic.sv
--- a/src_ref/core/pipeline/scr1_pipe_csr.sv
+++ b/src_ref/core/pipeline/scr1_pipe_csr.sv
--- a/src_ref/core/pipeline/scr1_pipe_exu.sv
+++ b/src_ref/core/pipeline/scr1_pipe_exu.sv
--- a/src_ref/core/pipeline/scr1_pipe_hdu.sv
+++ b/src_ref/core/pipeline/scr1_pipe_hdu.sv
--- a/src_ref/core/pipeline/scr1_pipe_ialu.sv
+++ b/src_ref/core/pipeline/scr1_pipe_ialu.sv
--- a/src_ref/core/pipeline/scr1_pipe_idu.sv
+++ b/src_ref/core/pipeline/scr1_pipe_idu.sv
--- a/src_ref/core/pipeline/scr1_pipe_ifu.sv
+++ b/src_ref/core/pipeline/scr1_pipe_ifu.sv
--- a/src_ref/core/pipeline/scr1_pipe_lsu.sv
+++ b/src_ref/core/pipeline/scr1_pipe_lsu.sv
--- a/src_ref/core/pipeline/scr1_pipe_mprf.sv
+++ b/src_ref/core/pipeline/scr1_pipe_mprf.sv
--- a/src_ref/core/pipeline/scr1_pipe_tdu.sv
+++ b/src_ref/core/pipeline/scr1_pipe_tdu.sv
--- a/src_ref/core/pipeline/scr1_pipe_top.sv
+++ b/src_ref/core/pipeline/scr1_pipe_top.sv
--- a/src_ref/core/pipeline/scr1_tracelog.sv
+++ b/src_ref/core/pipeline/scr1_tracelog.sv
--- a/src_ref/core/primitives/scr1_cg.sv
+++ b/src_ref/core/primitives/scr1_cg.sv
--- a/src_ref/core/primitives/scr1_reset_cells.sv
+++ b/src_ref/core/primitives/scr1_reset_cells.sv
--- a/src_ref/core/scr1_clk_ctrl.sv
+++ b/src_ref/core/scr1_clk_ctrl.sv
--- a/src_ref/core/scr1_core_top.sv
+++ b/src_ref/core/scr1_core_top.sv
--- a/src_ref/core/scr1_dm.sv
+++ b/src_ref/core/scr1_dm.sv
--- a/src_ref/core/scr1_dmi.sv
+++ b/src_ref/core/scr1_dmi.sv
--- a/src_ref/core/scr1_scu.sv
+++ b/src_ref/core/scr1_scu.sv
--- a/src_ref/core/scr1_tapc.sv
+++ b/src_ref/core/scr1_tapc.sv
--- a/src_ref/core/scr1_tapc_shift_reg.sv
+++ b/src_ref/core/scr1_tapc_shift_reg.sv
--- a/src_ref/core/scr1_tapc_synchronizer.sv
+++ b/src_ref/core/scr1_tapc_synchronizer.sv
--- a/src_ref/includes/scr1_ahb.svh
+++ b/src_ref/includes/scr1_ahb.svh
--- a/src_ref/includes/scr1_arch_description.svh
+++ b/src_ref/includes/scr1_arch_description.svh
--- a/src_ref/includes/scr1_arch_types.svh
+++ b/src_ref/includes/scr1_arch_types.svh
--- a/src_ref/includes/scr1_csr.svh
+++ b/src_ref/includes/scr1_csr.svh
--- a/src_ref/includes/scr1_dm.svh
+++ b/src_ref/includes/scr1_dm.svh
--- a/src_ref/includes/scr1_hdu.svh
+++ b/src_ref/includes/scr1_hdu.svh
--- a/src_ref/includes/scr1_ipic.svh
+++ b/src_ref/includes/scr1_ipic.svh
--- a/src_ref/includes/scr1_memif.svh
+++ b/src_ref/includes/scr1_memif.svh
--- a/src_ref/includes/scr1_riscv_isa_decoding.svh
+++ b/src_ref/includes/scr1_riscv_isa_decoding.svh
--- a/src_ref/includes/scr1_scu.svh
+++ b/src_ref/includes/scr1_scu.svh
--- a/src_ref/includes/scr1_search_ms1.svh
+++ b/src_ref/includes/scr1_search_ms1.svh
--- a/src_ref/includes/scr1_tapc.svh
+++ b/src_ref/includes/scr1_tapc.svh
--- a/src_ref/includes/scr1_tdu.svh
+++ b/src_ref/includes/scr1_tdu.svh
--- a/src_ref/rtl/filelist.v
+++ b/src_ref/rtl/filelist.v
@@ -1,39 +1,8 @@
-#`include "../scr1_custom_define.svh"
-#`include "../scr1_arch_custom.svh"
+// `include "../scr1_custom_define.svh"
+// `include "../scr1_arch_custom.svh"

-# core
-#/home/yenuchenko/riscv_school/scr1/scr1-master/src/core
-`include "../core/scr1_clk_ctrl.sv"
-`include "../core/scr1_core_top.sv"
-`include "../core/scr1_dm.sv"
-`include "../core/scr1_dmi.sv"
-`include "../core/scr1_scu.sv"
-`include "../core/scr1_tapc.sv"
-`include "../core/scr1_tapc_shift_reg.sv"
-`include "../core/scr1_tapc_synchronizer.sv"
-
-# pipeline
-#/home/yenuchenko/riscv_school/scr1/scr1-master/src/core/pipeline
-`include "../core/pipeline/scr1_ipic.sv"
-`include "../core/pipeline/scr1_pipe_csr.sv"
-`include "../core/pipeline/scr1_pipe_exu.sv"
-`include "../core/pipeline/scr1_pipe_hdu.sv"
-`include "../core/pipeline/scr1_pipe_ialu.sv"
-`include "../core/pipeline/scr1_pipe_idu.sv"
-`include "../core/pipeline/scr1_pipe_ifu.sv"
-`include "../core/pipeline/scr1_pipe_lsu.sv"
-`include "../core/pipeline/scr1_pipe_mprf.sv"
-`include "../core/pipeline/scr1_pipe_tdu.sv"
-`include "../core/pipeline/scr1_pipe_top.sv"
-`include "../core/pipeline/scr1_tracelog.sv"
-
-# primitives
-#/home/yenuchenko/riscv_school/scr1/scr1-master/src/core/primitives
-`include "../core/primitives/scr1_cg.sv"
-`include "../core/primitives/scr1_reset_cells.sv"
-
-# includes
-#/home/yenuchenko/riscv_school/scr1/scr1-master/src/includes
+// includes
+// /home/yenuchenko/riscv_school/scr1/scr1-master/src/includes
 `include "../includes/scr1_ahb.svh"
 `include "../includes/scr1_arch_description.svh"
 `include "../includes/scr1_arch_types.svh"
@@ -48,8 +17,39 @@
 `include "../includes/scr1_tapc.svh"
 `include "../includes/scr1_tdu.svh"

-# top
-#/home/yenuchenko/riscv_school/scr1/scr1-master/src/top
+// core
+// /home/yenuchenko/riscv_school/scr1/scr1-master/src/core
+`include "../core/scr1_clk_ctrl.sv"
+`include "../core/scr1_core_top.sv"
+`include "../core/scr1_dm.sv"
+`include "../core/scr1_dmi.sv"
+`include "../core/scr1_scu.sv"
+`include "../core/scr1_tapc.sv"
+`include "../core/scr1_tapc_shift_reg.sv"
+`include "../core/scr1_tapc_synchronizer.sv"
+
+// pipeline
+// /home/yenuchenko/riscv_school/scr1/scr1-master/src/core/pipeline
+`include "../core/pipeline/scr1_ipic.sv"
+`include "../core/pipeline/scr1_pipe_csr.sv"
+`include "../core/pipeline/scr1_pipe_exu.sv"
+`include "../core/pipeline/scr1_pipe_hdu.sv"
+`include "../core/pipeline/scr1_pipe_ialu.sv"
+`include "../core/pipeline/scr1_pipe_idu.sv"
+`include "../core/pipeline/scr1_pipe_ifu.sv"
+`include "../core/pipeline/scr1_pipe_lsu.sv"
+`include "../core/pipeline/scr1_pipe_mprf.sv"
+`include "../core/pipeline/scr1_pipe_tdu.sv"
+`include "../core/pipeline/scr1_pipe_top.sv"
+`include "../core/pipeline/scr1_tracelog.sv"
+
+// primitives
+// /home/yenuchenko/riscv_school/scr1/scr1-master/src/core/primitives
+`include "../core/primitives/scr1_cg.sv"
+`include "../core/primitives/scr1_reset_cells.sv"
+
+// top
+// /home/yenuchenko/riscv_school/scr1/scr1-master/src/top
 `include "../top/scr1_dmem_ahb.sv"
 `include "../top/scr1_dmem_router.sv"
 `include "../top/scr1_dp_memory.sv"
--- a/src_ref/sdc/scr1_top_ahb.sdc
+++ b/src_ref/sdc/scr1_top_ahb.sdc
--- a/src_ref/tb/scr1_memory_tb_ahb.sv
+++ b/src_ref/tb/scr1_memory_tb_ahb.sv
--- a/src_ref/tb/scr1_memory_tb_axi.sv
+++ b/src_ref/tb/scr1_memory_tb_axi.sv
--- a/src_ref/tb/scr1_top_tb_ahb.sv
+++ b/src_ref/tb/scr1_top_tb_ahb.sv
--- a/src_ref/tb/scr1_top_tb_axi.sv
+++ b/src_ref/tb/scr1_top_tb_axi.sv
--- a/src_ref/tb/scr1_top_tb_runtests.sv
+++ b/src_ref/tb/scr1_top_tb_runtests.sv
--- a/src_ref/top/scr1_dmem_ahb.sv
+++ b/src_ref/top/scr1_dmem_ahb.sv
--- a/src_ref/top/scr1_dmem_router.sv
+++ b/src_ref/top/scr1_dmem_router.sv
--- a/src_ref/top/scr1_dp_memory.sv
+++ b/src_ref/top/scr1_dp_memory.sv
--- a/src_ref/top/scr1_imem_ahb.sv
+++ b/src_ref/top/scr1_imem_ahb.sv
--- a/src_ref/top/scr1_imem_router.sv
+++ b/src_ref/top/scr1_imem_router.sv
--- a/src_ref/top/scr1_mem_axi.sv
+++ b/src_ref/top/scr1_mem_axi.sv
--- a/src_ref/top/scr1_tcm.sv
+++ b/src_ref/top/scr1_tcm.sv
--- a/src_ref/top/scr1_timer.sv
+++ b/src_ref/top/scr1_timer.sv
--- a/src_ref/top/scr1_top_ahb.sv
+++ b/src_ref/top/scr1_top_ahb.sv
--- a/src_ref/top/scr1_top_axi.sv
+++ b/src_ref/top/scr1_top_axi.sv