107 lines
3.4 KiB
Tcl
107 lines
3.4 KiB
Tcl
### Stage: "Synthesis and PaR"
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### File description: "Constraints for the design"
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# SET LIB UNITS
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set_units -time 1.0ns;
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set_units -capacitance 1.0pF;
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set_max_capacitance 0.5 [all_outputs]
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### ====================== CLOCKS ===========================
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#clock uncertainty: 200ps for all clocks
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set CLK_UNCERT 0.2;
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#transition: 1ns R/F
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# CLOCK PERIOD
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set CLK_PERIOD 11.13
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set TCK_PERIOD 100
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set RTC_CLK_PERIOD 10000
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# IO DELAYS
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set INPUT_DELAY_CLK [expr $CLK_PERIOD/4.0]
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set OUTPUT_DELAY_CLK [expr $CLK_PERIOD/4.0]
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set INPUT_DELAY_TCK [expr $TCK_PERIOD/4.0]
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set OUTPUT_DELAY_TCK [expr $TCK_PERIOD/4.0]
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#clk->100MHz
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create_clock -name "clk" -period $CLK_PERIOD -waveform "0 [expr $CLK_PERIOD/2.0]" [get_ports "clk"]
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#tck->10MHz
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create_clock -name "tck" -period $TCK_PERIOD -waveform "0 [expr $TCK_PERIOD/2.0]" [get_ports "tck"]
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#rtc_clk->100kHz
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create_clock -name "rtc_clk" -period $RTC_CLK_PERIOD -waveform "0 [expr $RTC_CLK_PERIOD/2.0]" [get_ports "rtc_clk"]
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set_clock_groups -asynchronous -group {"clk"} -group {"tck"} -group {"rtc_clk"}
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set MINRISE 0
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set MAXRISE 1.0
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set MINFALL 0
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set MAXFALL 1.0
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set_clock_uncertainty $CLK_UNCERT [get_clocks "clk"]
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set_clock_transition -rise -min $MINRISE [get_clocks "clk"]
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set_clock_transition -rise -max $MAXRISE [get_clocks "clk"]
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set_clock_transition -fall -min $MINFALL [get_clocks "clk"]
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set_clock_transition -fall -max $MAXFALL [get_clocks "clk"]
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set_clock_uncertainty $CLK_UNCERT [get_clocks "tck"]
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set_clock_transition -rise -min $MINRISE [get_clocks "tck"]
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set_clock_transition -rise -max $MAXRISE [get_clocks "tck"]
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set_clock_transition -fall -min $MINFALL [get_clocks "tck"]
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set_clock_transition -fall -max $MAXFALL [get_clocks "tck"]
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set_clock_uncertainty $CLK_UNCERT [get_clocks "rtc_clk"]
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set_clock_transition -rise -min $MINRISE [get_clocks "rtc_clk"]
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set_clock_transition -rise -max $MAXRISE [get_clocks "rtc_clk"]
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set_clock_transition -fall -min $MINFALL [get_clocks "rtc_clk"]
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set_clock_transition -fall -max $MAXFALL [get_clocks "rtc_clk"]
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set_ideal_network [get_ports "pwrup_rst_n"]
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set_ideal_network [get_ports "rst_n"]
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set_ideal_network [get_ports "cpu_rst_n"]
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set_ideal_network [get_ports "test_rst_n"]
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set_ideal_network [get_ports "trst_n"]
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set_false_path -from [get_ports "pwrup_rst_n"]
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set_false_path -from [get_ports "rst_n"]
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set_false_path -from [get_ports "cpu_rst_n"]
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set_false_path -from [get_ports "test_rst_n"]
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set_false_path -from [get_ports "trst_n"]
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#IO delays:
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set_input_delay -clock "clk" -max $INPUT_DELAY_CLK [remove_from_collection [all_inputs] {trst_n tdi tms}]
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set_input_delay -clock "clk" -min $INPUT_DELAY_CLK [remove_from_collection [all_inputs] {trst_n tdi tms}]
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set_input_delay -clock "tck" -max $INPUT_DELAY_TCK [get_ports {trst_n tdi tms}]
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set_input_delay -clock "tck" -min $INPUT_DELAY_TCK [get_ports {trst_n tdi tms}]
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set_output_delay -clock "clk" -max $OUTPUT_DELAY_CLK [remove_from_collection [all_outputs] {tdo tdo_en}]
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set_output_delay -clock "clk" -min $OUTPUT_DELAY_CLK [remove_from_collection [all_outputs] {tdo tdo_en}]
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set_output_delay -clock "tck" -max $OUTPUT_DELAY_TCK [get_ports {tdo tdo_en}]
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set_output_delay -clock "tck" -min $OUTPUT_DELAY_TCK [get_ports {tdo tdo_en}]
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set_case_analysis 0 [get_ports "test_mode"]
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# |--------------|
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#->| |->
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#->| clk |->
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# | |
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# ----------------
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# | rtc |
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# ----------------
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#->| |->tdo
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#->| tck |->tdo_en
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# | |
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# |--------------|
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