88 lines
3.3 KiB
Tcl
88 lines
3.3 KiB
Tcl
### Technology: "X-FAB 180 nm CMOS, XT018 1243"
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### Library: "D_CELLS_HD, 1.8V"
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### Tools: "Cadence Encounter"
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###
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### Stage: "PaR"
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### File description: "Multi-mode multi-corner (MMMC) file for the Cadence Encounter EDA tool"
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## Timing constraints file from the synthesis
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create_constraint_mode -name CONSTRAINTS -sdc_files {../Source/Constraints_synth_typ.sdc}
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## Create timing libraries sets
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# The slowest corner
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create_library_set -name SLOWlib \
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-timing {/Cadence/Libs/X_FAB/XKIT/xt018/diglibs/D_CELLS_HD/v4_0/liberty_LP5MOS/v4_0_0/PVT_1_80V_range/D_CELLS_HD_LP5MOS_slow_1_62V_175C.lib}
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# Typical corner
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create_library_set -name TYPlib \
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-timing {/Cadence/Libs/X_FAB/XKIT/xt018/diglibs/D_CELLS_HD/v4_0/liberty_LP5MOS/v4_0_0/PVT_1_80V_range/D_CELLS_HD_LP5MOS_typ_1_80V_25C.lib}
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# The fastest corner
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create_library_set -name FASTlib \
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-timing {/Cadence/Libs/X_FAB/XKIT/xt018/diglibs/D_CELLS_HD/v4_0/liberty_LP5MOS/v4_0_0/PVT_1_80V_range/D_CELLS_HD_LP5MOS_fast_1_98V_m40C.lib}
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## Create operating conditions (P-V-T) for the timing libraries (CAN BE ABSENT IF CONDITIONS ARE GENERAL)
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# The slowest operation condition
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create_op_cond -name PVT_slow_1_62V_175C \
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-library_file {/Cadence/Libs/X_FAB/XKIT/xt018/diglibs/D_CELLS_HD/v4_0/liberty_LP5MOS/v4_0_0/PVT_1_80V_range/D_CELLS_HD_LP5MOS_slow_1_62V_175C.lib} \
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-P {1} -V {1.62} -T {175}
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# Typical operation condition
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create_op_cond -name PVT_typ_1_80V_25C \
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-library_file {/Cadence/Libs/X_FAB/XKIT/xt018/diglibs/D_CELLS_HD/v4_0/liberty_LP5MOS/v4_0_0/PVT_1_80V_range/D_CELLS_HD_LP5MOS_typ_1_80V_25C.lib} \
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-P {1} -V {1.8} -T {25}
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# The fastest operation condition
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create_op_cond -name PVT_fast_1_98V_-40C \
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-library_file {/Cadence/Libs/X_FAB/XKIT/xt018/diglibs/D_CELLS_HD/v4_0/liberty_LP5MOS/v4_0_0/PVT_1_80V_range/D_CELLS_HD_LP5MOS_fast_1_98V_m40C.lib} \
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-P {1} -V {1.98} -T {-40}
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## Create RC corner(s) from capacitance table(s)
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create_rc_corner -name RCcornerMIN \
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-cap_table /Cadence/Libs/X_FAB/XKIT/xt018/cadence/v7_0/capTbl/v7_0_1/xt018_xx43_MET4_METMID_METTHK_min.capTbl \
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-qx_tech_file /Cadence/Libs/X_FAB/XKIT/xt018/cadence/v7_0/QRC_pvs/v7_0_3/XT018_1243/QRC-Min/qrcTechFile
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create_rc_corner -name RCcornerTYP \
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-cap_table /Cadence/Libs/X_FAB/XKIT/xt018/cadence/v7_0/capTbl/v7_0_1/xt018_xx43_MET4_METMID_METTHK_typ.capTbl \
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-qx_tech_file /Cadence/Libs/X_FAB/XKIT/xt018/cadence/v7_0/QRC_pvs/v7_0_3/XT018_1243/QRC-Typ/qrcTechFile
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create_rc_corner -name RCcornerMAX \
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-cap_table /Cadence/Libs/X_FAB/XKIT/xt018/cadence/v7_0/capTbl/v7_0_1/xt018_xx43_MET4_METMID_METTHK_max.capTbl \
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-qx_tech_file /Cadence/Libs/X_FAB/XKIT/xt018/cadence/v7_0/QRC_pvs/v7_0_3/XT018_1243/QRC-Max/qrcTechFile
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## Create delay corner(s)
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create_delay_corner -name DELAYcornerSLOW \
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-library_set SLOWlib \
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-rc_corner RCcornerMAX
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create_delay_corner -name DELAYcornerTYP \
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-library_set TYPlib \
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-rc_corner RCcornerTYP
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create_delay_corner -name DELAYcornerFAST \
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-library_set FASTlib \
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-rc_corner RCcornerMIN
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## Create analysis views
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create_analysis_view -name MAXview \
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-delay_corner {DELAYcornerSLOW} \
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-constraint_mode {CONSTRAINTS}
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create_analysis_view -name TYPview \
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-delay_corner {DELAYcornerTYP} \
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-constraint_mode {CONSTRAINTS}
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create_analysis_view -name MINview \
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-delay_corner {DELAYcornerFAST} \
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-constraint_mode {CONSTRAINTS}
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## Set analysis view to above for both setup and hold
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set_analysis_view -setup {TYPview} -hold {TYPview}
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