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riscv_school_scr1/src/axi_tb.files
Mikhail Yenuchenko c8ab0ca4f7 Init
2026-01-20 16:23:00 +03:00

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core/pipeline/scr1_tracelog.sv
tb/scr1_memory_tb_axi.sv
tb/scr1_top_tb_axi.sv