50 lines
1.5 KiB
Systemverilog
50 lines
1.5 KiB
Systemverilog
/// Copyright by Syntacore LLC © 2016-2021. See LICENSE for details
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/// @file <scr1_memif.svh>
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/// @brief Memory interface definitions file
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///
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`ifndef SCR1_MEMIF_SVH
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`define SCR1_MEMIF_SVH
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`include "scr1_arch_description.svh"
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//-------------------------------------------------------------------------------
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// Memory command enum
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//-------------------------------------------------------------------------------
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typedef enum logic {
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SCR1_MEM_CMD_RD = 1'b0,
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SCR1_MEM_CMD_WR = 1'b1
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`ifdef SCR1_XPROP_EN
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,
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SCR1_MEM_CMD_ERROR = 'x
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`endif // SCR1_XPROP_EN
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} type_scr1_mem_cmd_e;
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//-------------------------------------------------------------------------------
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// Memory data width enum
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//-------------------------------------------------------------------------------
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typedef enum logic[1:0] {
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SCR1_MEM_WIDTH_BYTE = 2'b00,
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SCR1_MEM_WIDTH_HWORD = 2'b01,
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SCR1_MEM_WIDTH_WORD = 2'b10
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`ifdef SCR1_XPROP_EN
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,
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SCR1_MEM_WIDTH_ERROR = 'x
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`endif // SCR1_XPROP_EN
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} type_scr1_mem_width_e;
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//-------------------------------------------------------------------------------
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// Memory response enum
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//-------------------------------------------------------------------------------
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typedef enum logic[1:0] {
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SCR1_MEM_RESP_NOTRDY = 2'b00,
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SCR1_MEM_RESP_RDY_OK = 2'b01,
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SCR1_MEM_RESP_RDY_ER = 2'b10
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`ifdef SCR1_XPROP_EN
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,
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SCR1_MEM_RESP_ERROR = 'x
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`endif // SCR1_XPROP_EN
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} type_scr1_mem_resp_e;
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`endif // SCR1_MEMIF_SVH
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