27 lines
1.1 KiB
Tcl
27 lines
1.1 KiB
Tcl
### Technology: "X-FAB 180 nm CMOS, XT018 1243"
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### Library: "D_CELLS_HD, 1.8V"
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### Tools: "Cadence RTL Compiler"
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###
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### Stage: "Synthesis"
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### File description: "Contains paths to the library of digital cells (slow corner)"
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# Setup path for liberty CPF directory
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set_attribute lib_search_path /Cadence/Libs/X_FAB/XKIT/xt018/diglibs/D_CELLS_HD/v4_0/liberty_LP5MOS/v4_0_0/PVT_1_80V_range
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# Setup PVT corner .lib file
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set_attribute library {/Cadence/Libs/X_FAB/XKIT/xt018/diglibs/D_CELLS_HD/v4_0/liberty_LP5MOS/v4_0_0/PVT_1_80V_range/D_CELLS_HD_LP5MOS_fast_1_98V_m40C.lib}
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# Setup LEF files
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set_attribute lef_library { \
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/Cadence/Libs/X_FAB/XKIT/xt018/cadence/v7_0/techLEF/v7_0_1_1/xt018_xx43_MET4_METMID_METTHK.lef \
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/Cadence/Libs/X_FAB/XKIT/xt018/diglibs/D_CELLS_HD/v4_0/LEF/v4_0_0/xt018_D_CELLS_HD.lef \
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/Cadence/Libs/X_FAB/XKIT/xt018/diglibs/D_CELLS_HD/v4_0/LEF/v4_0_0/xt018_xx43_MET4_METMID_METTHK_D_CELLS_HD_mprobe.lef \
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}
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# Setup capacitance table file
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set_attribute cap_table_file /Cadence/Libs/X_FAB/XKIT/xt018/cadence/v7_0/capTbl/v7_0_1/xt018_xx43_MET4_METMID_METTHK_fast.capTbl
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# Setup error on blackbox
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set_attribute hdl_error_on_blackbox true
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