60 lines
1.7 KiB
Systemverilog
60 lines
1.7 KiB
Systemverilog
/// Copyright by Syntacore LLC © 2016-2021. See LICENSE for details
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/// @file <scr1_ahb.svh>
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/// @brief AHB header file
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///
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`ifndef SCR1_AHB_SVH
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`define SCR1_AHB_SVH
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`include "scr1_arch_description.svh"
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parameter SCR1_AHB_WIDTH = 32;
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// Encoding for HTRANS signal
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parameter logic [1:0] SCR1_HTRANS_IDLE = 2'b00;
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parameter logic [1:0] SCR1_HTRANS_NONSEQ = 2'b10;
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`ifdef SCR1_XPROP_EN
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parameter logic [1:0] SCR1_HTRANS_ERR = 'x;
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`else // SCR1_XPROP_EN
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parameter logic [1:0] SCR1_HTRANS_ERR = '0;
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`endif // SCR1_XPROP_EN
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// Encoding for HBURST signal
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parameter logic [2:0] SCR1_HBURST_SINGLE = 3'b000;
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`ifdef SCR1_XPROP_EN
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parameter logic [2:0] SCR1_HBURST_ERR = 'x;
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`else // SCR1_XPROP_EN
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parameter logic [1:0] SCR1_HBURST_ERR = '0;
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`endif // SCR1_XPROP_EN
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// Encoding for HSIZE signal
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parameter logic [2:0] SCR1_HSIZE_8B = 3'b000;
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parameter logic [2:0] SCR1_HSIZE_16B = 3'b001;
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parameter logic [2:0] SCR1_HSIZE_32B = 3'b010;
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`ifdef SCR1_XPROP_EN
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parameter logic [2:0] SCR1_HSIZE_ERR = 'x;
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`else // SCR1_XPROP_EN
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parameter logic [2:0] SCR1_HSIZE_ERR = '0;
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`endif // SCR1_XPROP_EN
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// Encoding HPROT signal
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// HPROT[0] : 0 - instr; 1 - data
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// HPROT[1] : 0 - user; 1 - privilege
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// HPROT[2] : 0 - not buffer; 1 - buffer
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// HPROT[3] : 0 - cacheable; 1 - cacheable
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parameter SCR1_HPROT_DATA = 0;
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parameter SCR1_HPROT_PRV = 1;
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parameter SCR1_HPROT_BUF = 2;
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parameter SCR1_HPROT_CACHE = 3;
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// Encoding HRESP signal
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parameter logic SCR1_HRESP_OKAY = 1'b0;
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parameter logic SCR1_HRESP_ERROR = 1'b1;
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`ifdef SCR1_XPROP_EN
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parameter logic SCR1_HRESP_ERR = 1'bx;
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`else // SCR1_XPROP_EN
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parameter logic SCR1_HRESP_ERR = 1'b0;
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`endif // SCR1_XPROP_EN
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`endif // SCR1_AHB_SVH
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