155 lines
3.4 KiB
ArmAsm
155 lines
3.4 KiB
ArmAsm
/// Copyright by Syntacore LLC © 2016, 2017. See LICENSE for details
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/// @file <crt_tcm.S>
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///
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#include "riscv_csr_encoding.h"
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#include "reloc.h"
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#include "sc_test.h"
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# define LREG lw
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# define SREG sw
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# define REGBYTES 4
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.globl _start
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.globl main
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.globl trap_entry
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.globl handle_trap
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.globl sc_exit
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.weak trap_entry, handle_trap
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.section .text.init
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.org (64*3)
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.align 6;
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machine_trap_entry:
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j trap_entry
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.align 6
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_start:
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#ifndef __RVE_EXT
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zero_int_regs 1, 31
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#else
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zero_int_regs 1, 15
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#endif
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# Global pointer init
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.option push
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.option norelax
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la gp, __global_pointer$
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.option pop
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RELOC_PROC;
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// init tdata
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mv a1, tp
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la a2, _tdata_end
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j 6f
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5: lw a3, 0(a0)
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sw a3, 0(a1)
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add a0, a0, 4
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add a1, a1, 4
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6: bne a0, a2, 5b
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// clear tbss
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j 8f
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7: sw zero, 0(a1)
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add a1, a1, 4
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8: bne a1, a4, 7b
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// Timer init
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li t0, mtime_ctrl
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li t1, (1 << SCR1_MTIME_CTRL_EN) // enable, use internal clock
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sw t1, (t0)
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li t0, mtime_div
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li t1, (100-1) // divide by 100
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sw t1, (t0)
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li t0, mtimecmp
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li t1, -1
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sw t1, (t0) // max value for mtimecmp
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sw t1, 4(t0)
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li a0, 0
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li a1, 0
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call main
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tail sc_exit
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trap_entry:
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addi sp, sp, -272
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SREG x1, 1*REGBYTES(sp)
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SREG x2, 2*REGBYTES(sp)
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SREG x3, 3*REGBYTES(sp)
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SREG x4, 4*REGBYTES(sp)
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SREG x5, 5*REGBYTES(sp)
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SREG x6, 6*REGBYTES(sp)
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SREG x7, 7*REGBYTES(sp)
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SREG x8, 8*REGBYTES(sp)
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SREG x9, 9*REGBYTES(sp)
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SREG x10, 10*REGBYTES(sp)
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SREG x11, 11*REGBYTES(sp)
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SREG x12, 12*REGBYTES(sp)
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SREG x13, 13*REGBYTES(sp)
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SREG x14, 14*REGBYTES(sp)
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SREG x15, 15*REGBYTES(sp)
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#ifndef __RVE_EXT
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SREG x16, 16*REGBYTES(sp)
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SREG x17, 17*REGBYTES(sp)
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SREG x18, 18*REGBYTES(sp)
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SREG x19, 19*REGBYTES(sp)
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SREG x20, 20*REGBYTES(sp)
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SREG x21, 21*REGBYTES(sp)
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SREG x22, 22*REGBYTES(sp)
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SREG x23, 23*REGBYTES(sp)
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SREG x24, 24*REGBYTES(sp)
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SREG x25, 25*REGBYTES(sp)
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SREG x26, 26*REGBYTES(sp)
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SREG x27, 27*REGBYTES(sp)
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SREG x28, 28*REGBYTES(sp)
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SREG x29, 29*REGBYTES(sp)
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SREG x30, 30*REGBYTES(sp)
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SREG x31, 31*REGBYTES(sp)
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#endif // __RVE_EXT
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csrr a0, mcause
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csrr a1, mepc
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mv a2, sp
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call handle_trap
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LREG x1, 1*REGBYTES(sp)
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LREG x2, 2*REGBYTES(sp)
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LREG x3, 3*REGBYTES(sp)
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LREG x4, 4*REGBYTES(sp)
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LREG x5, 5*REGBYTES(sp)
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LREG x6, 6*REGBYTES(sp)
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LREG x7, 7*REGBYTES(sp)
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LREG x8, 8*REGBYTES(sp)
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LREG x9, 9*REGBYTES(sp)
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LREG x10, 10*REGBYTES(sp)
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LREG x11, 11*REGBYTES(sp)
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LREG x12, 12*REGBYTES(sp)
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LREG x13, 13*REGBYTES(sp)
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LREG x14, 14*REGBYTES(sp)
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LREG x15, 15*REGBYTES(sp)
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#ifndef __RVE_EXT
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LREG x16, 16*REGBYTES(sp)
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LREG x17, 17*REGBYTES(sp)
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LREG x18, 18*REGBYTES(sp)
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LREG x19, 19*REGBYTES(sp)
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LREG x20, 20*REGBYTES(sp)
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LREG x21, 21*REGBYTES(sp)
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LREG x22, 22*REGBYTES(sp)
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LREG x23, 23*REGBYTES(sp)
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LREG x24, 24*REGBYTES(sp)
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LREG x25, 25*REGBYTES(sp)
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LREG x26, 26*REGBYTES(sp)
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LREG x27, 27*REGBYTES(sp)
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LREG x28, 28*REGBYTES(sp)
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LREG x29, 29*REGBYTES(sp)
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LREG x30, 30*REGBYTES(sp)
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LREG x31, 31*REGBYTES(sp)
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#endif // __RVE_EXT
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addi sp, sp, 272
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mret
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handle_trap:
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j SIM_EXIT
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// end of crt.S |