454 lines
19 KiB
Systemverilog
454 lines
19 KiB
Systemverilog
/// Copyright by Syntacore LLC © 2016-2021. See LICENSE for details
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/// @file <scr1_tracelog.sv>
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/// @brief Core tracelog module
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///
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`include "scr1_arch_description.svh"
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`include "scr1_arch_types.svh"
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`include "scr1_csr.svh"
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`ifdef SCR1_TRGT_SIMULATION
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module scr1_tracelog (
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input logic rst_n, // Tracelog reset
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input logic clk // Tracelog clock
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`ifdef SCR1_TRACE_LOG_EN
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,
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input logic [`SCR1_XLEN-1:0] soc2pipe_fuse_mhartid_i, // Fuse MHARTID
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// MPRF
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`ifdef SCR1_MPRF_RAM
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input logic [`SCR1_XLEN-1:0] mprf2trace_int_i [1:`SCR1_MPRF_SIZE-1], // MPRF registers content
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`else // SCR1_MPRF_RAM
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input type_scr1_mprf_v [1:`SCR1_MPRF_SIZE-1] mprf2trace_int_i, // MPRF registers content
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`endif // SCR1_MPRF_RAM
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input logic mprf2trace_wr_en_i, // MPRF write enable
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input logic [`SCR1_MPRF_AWIDTH-1:0] mprf2trace_wr_addr_i, // MPRF write address
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input logic [`SCR1_XLEN-1:0] mprf2trace_wr_data_i, // MPRF write data
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// EXU
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input logic exu2trace_update_pc_en_i, // PC updated flag
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input logic [`SCR1_XLEN-1:0] exu2trace_update_pc_i, // Next PC value
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// IFU
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input logic [`SCR1_IMEM_DWIDTH-1:0] ifu2trace_instr_i, // Current instruction from IFU stage
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// CSR
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input logic csr2trace_mstatus_mie_i, // CSR MSTATUS.mie bit
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input logic csr2trace_mstatus_mpie_i, // CSR MSTATUS.mpie bit
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input logic [`SCR1_XLEN-1:6] csr2trace_mtvec_base_i, // CSR MTVEC.
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input logic csr2trace_mtvec_mode_i, // CSR MTVEC.
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input logic csr2trace_mie_meie_i, // CSR MIE.meie bit
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input logic csr2trace_mie_mtie_i, // CSR MIE.mtie bit
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input logic csr2trace_mie_msie_i, // CSR MIE.msie bit
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input logic csr2trace_mip_meip_i, // CSR MIP.meip bit
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input logic csr2trace_mip_mtip_i, // CSR MIP.mtip bit
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input logic csr2trace_mip_msip_i, // CSR MIP.msip bit
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`ifdef SCR1_RVC_EXT
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input logic [`SCR1_XLEN-1:1] csr2trace_mepc_i, // CSR MEPC register
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`else // SCR1_RVC_EXT
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input logic [`SCR1_XLEN-1:2] csr2trace_mepc_i, // CSR MEPC register
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`endif // SCR1_RVC_EXT
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input logic csr2trace_mcause_irq_i, // CSR MCAUSE.interrupt bit
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input type_scr1_exc_code_e csr2trace_mcause_ec_i, // CSR MCAUSE.exception_code bit
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input logic [`SCR1_XLEN-1:0] csr2trace_mtval_i, // CSR MTVAL register
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// Events
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input logic csr2trace_e_exc_i, // exception event
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input logic csr2trace_e_irq_i, // interrupt event
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input logic pipe2trace_e_wake_i // pipe wakeup event
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`endif // SCR1_TRACE_LOG_EN
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);
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//-------------------------------------------------------------------------------
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// Local types declaration
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//-------------------------------------------------------------------------------
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`ifdef SCR1_TRACE_LOG_EN
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typedef struct {
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logic [`SCR1_XLEN-1:0] INT_00_ZERO ;
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logic [`SCR1_XLEN-1:0] INT_01_RA ;
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logic [`SCR1_XLEN-1:0] INT_02_SP ;
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logic [`SCR1_XLEN-1:0] INT_03_GP ;
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logic [`SCR1_XLEN-1:0] INT_04_TP ;
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logic [`SCR1_XLEN-1:0] INT_05_T0 ;
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logic [`SCR1_XLEN-1:0] INT_06_T1 ;
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logic [`SCR1_XLEN-1:0] INT_07_T2 ;
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logic [`SCR1_XLEN-1:0] INT_08_S0 ;
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logic [`SCR1_XLEN-1:0] INT_09_S1 ;
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logic [`SCR1_XLEN-1:0] INT_10_A0 ;
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logic [`SCR1_XLEN-1:0] INT_11_A1 ;
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logic [`SCR1_XLEN-1:0] INT_12_A2 ;
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logic [`SCR1_XLEN-1:0] INT_13_A3 ;
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logic [`SCR1_XLEN-1:0] INT_14_A4 ;
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logic [`SCR1_XLEN-1:0] INT_15_A5 ;
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`ifndef SCR1_RVE_EXT
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logic [`SCR1_XLEN-1:0] INT_16_A6 ;
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logic [`SCR1_XLEN-1:0] INT_17_A7 ;
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logic [`SCR1_XLEN-1:0] INT_18_S2 ;
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logic [`SCR1_XLEN-1:0] INT_19_S3 ;
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logic [`SCR1_XLEN-1:0] INT_20_S4 ;
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logic [`SCR1_XLEN-1:0] INT_21_S5 ;
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logic [`SCR1_XLEN-1:0] INT_22_S6 ;
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logic [`SCR1_XLEN-1:0] INT_23_S7 ;
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logic [`SCR1_XLEN-1:0] INT_24_S8 ;
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logic [`SCR1_XLEN-1:0] INT_25_S9 ;
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logic [`SCR1_XLEN-1:0] INT_26_S10 ;
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logic [`SCR1_XLEN-1:0] INT_27_S11 ;
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logic [`SCR1_XLEN-1:0] INT_28_T3 ;
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logic [`SCR1_XLEN-1:0] INT_29_T4 ;
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logic [`SCR1_XLEN-1:0] INT_30_T5 ;
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logic [`SCR1_XLEN-1:0] INT_31_T6 ;
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`endif // SCR1_RVE_EXT
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} type_scr1_ireg_name_s;
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typedef struct packed {
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logic [`SCR1_XLEN-1:0] mstatus;
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logic [`SCR1_XLEN-1:0] mtvec;
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logic [`SCR1_XLEN-1:0] mie;
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logic [`SCR1_XLEN-1:0] mip;
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logic [`SCR1_XLEN-1:0] mepc;
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logic [`SCR1_XLEN-1:0] mcause;
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logic [`SCR1_XLEN-1:0] mtval;
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} type_scr1_csr_trace_s;
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`endif // SCR1_TRACE_LOG_EN
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//-------------------------------------------------------------------------------
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// Local Signal Declaration
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//-------------------------------------------------------------------------------
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`ifdef SCR1_TRACE_LOG_EN
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type_scr1_ireg_name_s mprf_int_alias;
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time current_time;
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// Tracelog control signals
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logic trace_flag;
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logic trace_update;
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logic trace_update_r;
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byte event_type;
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logic [`SCR1_XLEN-1:0] trace_pc;
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logic [`SCR1_XLEN-1:0] trace_npc;
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logic [`SCR1_IMEM_DWIDTH-1:0] trace_instr;
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type_scr1_csr_trace_s csr_trace1;
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// File handlers
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int unsigned trace_fhandler_core;
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// MPRF signals
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logic mprf_up;
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logic [`SCR1_MPRF_AWIDTH-1:0] mprf_addr;
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logic [`SCR1_XLEN-1:0] mprf_wdata;
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string hart;
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string test_name;
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`endif // SCR1_TRACE_LOG_EN
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//-------------------------------------------------------------------------------
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// Local tasks
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//-------------------------------------------------------------------------------
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`ifdef SCR1_TRACE_LOG_EN
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task trace_write_common;
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$fwrite(trace_fhandler_core, "%16d ", current_time);
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// $fwrite(trace_fhandler_core, " 0 ");
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$fwrite(trace_fhandler_core, " %s ", event_type);
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$fwrite(trace_fhandler_core, " %8x ", trace_pc);
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$fwrite(trace_fhandler_core, " %8x ", trace_instr);
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$fwrite(trace_fhandler_core, " %8x ", trace_npc);
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endtask // trace_write_common
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task trace_write_int_walias;
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case (mprf_addr)
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0 : $fwrite(trace_fhandler_core, " x00_zero ");
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1 : $fwrite(trace_fhandler_core, " x01_ra ");
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2 : $fwrite(trace_fhandler_core, " x02_sp ");
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3 : $fwrite(trace_fhandler_core, " x03_gp ");
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4 : $fwrite(trace_fhandler_core, " x04_tp ");
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5 : $fwrite(trace_fhandler_core, " x05_t0 ");
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6 : $fwrite(trace_fhandler_core, " x06_t1 ");
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7 : $fwrite(trace_fhandler_core, " x07_t2 ");
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8 : $fwrite(trace_fhandler_core, " x08_s0 ");
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9 : $fwrite(trace_fhandler_core, " x09_s1 ");
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10 : $fwrite(trace_fhandler_core, " x10_a0 ");
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11 : $fwrite(trace_fhandler_core, " x11_a1 ");
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12 : $fwrite(trace_fhandler_core, " x12_a2 ");
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13 : $fwrite(trace_fhandler_core, " x13_a3 ");
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14 : $fwrite(trace_fhandler_core, " x14_a4 ");
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15 : $fwrite(trace_fhandler_core, " x15_a5 ");
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`ifndef SCR1_RVE_EXT
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16 : $fwrite(trace_fhandler_core, " x16_a6 ");
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17 : $fwrite(trace_fhandler_core, " x17_a7 ");
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18 : $fwrite(trace_fhandler_core, " x18_s2 ");
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19 : $fwrite(trace_fhandler_core, " x19_s3 ");
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20 : $fwrite(trace_fhandler_core, " x20_s4 ");
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21 : $fwrite(trace_fhandler_core, " x21_s5 ");
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22 : $fwrite(trace_fhandler_core, " x22_s6 ");
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23 : $fwrite(trace_fhandler_core, " x23_s7 ");
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24 : $fwrite(trace_fhandler_core, " x24_s8 ");
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25 : $fwrite(trace_fhandler_core, " x25_s9 ");
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26 : $fwrite(trace_fhandler_core, " x26_s10 ");
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27 : $fwrite(trace_fhandler_core, " x27_s11 ");
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28 : $fwrite(trace_fhandler_core, " x28_t3 ");
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29 : $fwrite(trace_fhandler_core, " x29_t4 ");
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30 : $fwrite(trace_fhandler_core, " x30_t5 ");
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31 : $fwrite(trace_fhandler_core, " x31_t6 ");
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`endif // SCR1_RVE_EXT
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default: begin
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$fwrite(trace_fhandler_core, " xxx ");
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end
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endcase
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endtask
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//-------------------------------------------------------------------------------
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// MPRF Registers assignment
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//-------------------------------------------------------------------------------
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assign mprf_int_alias.INT_00_ZERO = '0;
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assign mprf_int_alias.INT_01_RA = mprf2trace_int_i[1];
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assign mprf_int_alias.INT_02_SP = mprf2trace_int_i[2];
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assign mprf_int_alias.INT_03_GP = mprf2trace_int_i[3];
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assign mprf_int_alias.INT_04_TP = mprf2trace_int_i[4];
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assign mprf_int_alias.INT_05_T0 = mprf2trace_int_i[5];
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assign mprf_int_alias.INT_06_T1 = mprf2trace_int_i[6];
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assign mprf_int_alias.INT_07_T2 = mprf2trace_int_i[7];
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assign mprf_int_alias.INT_08_S0 = mprf2trace_int_i[8];
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assign mprf_int_alias.INT_09_S1 = mprf2trace_int_i[9];
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assign mprf_int_alias.INT_10_A0 = mprf2trace_int_i[10];
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assign mprf_int_alias.INT_11_A1 = mprf2trace_int_i[11];
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assign mprf_int_alias.INT_12_A2 = mprf2trace_int_i[12];
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assign mprf_int_alias.INT_13_A3 = mprf2trace_int_i[13];
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assign mprf_int_alias.INT_14_A4 = mprf2trace_int_i[14];
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assign mprf_int_alias.INT_15_A5 = mprf2trace_int_i[15];
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`ifndef SCR1_RVE_EXT
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assign mprf_int_alias.INT_16_A6 = mprf2trace_int_i[16];
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assign mprf_int_alias.INT_17_A7 = mprf2trace_int_i[17];
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assign mprf_int_alias.INT_18_S2 = mprf2trace_int_i[18];
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assign mprf_int_alias.INT_19_S3 = mprf2trace_int_i[19];
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assign mprf_int_alias.INT_20_S4 = mprf2trace_int_i[20];
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assign mprf_int_alias.INT_21_S5 = mprf2trace_int_i[21];
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assign mprf_int_alias.INT_22_S6 = mprf2trace_int_i[22];
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assign mprf_int_alias.INT_23_S7 = mprf2trace_int_i[23];
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assign mprf_int_alias.INT_24_S8 = mprf2trace_int_i[24];
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assign mprf_int_alias.INT_25_S9 = mprf2trace_int_i[25];
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assign mprf_int_alias.INT_26_S10 = mprf2trace_int_i[26];
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assign mprf_int_alias.INT_27_S11 = mprf2trace_int_i[27];
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assign mprf_int_alias.INT_28_T3 = mprf2trace_int_i[28];
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assign mprf_int_alias.INT_29_T4 = mprf2trace_int_i[29];
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assign mprf_int_alias.INT_30_T5 = mprf2trace_int_i[30];
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assign mprf_int_alias.INT_31_T6 = mprf2trace_int_i[31];
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`endif // SCR1_RVE_EXT
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`endif // SCR1_TRACE_LOG_EN
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//-------------------------------------------------------------------------------
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// Legacy time counter
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//-------------------------------------------------------------------------------
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// The counter is left for compatibility with the current UVM environment
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int time_cnt;
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always_ff @(negedge rst_n, posedge clk) begin
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if (~rst_n) begin
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time_cnt <= 0;
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end else begin
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time_cnt <= time_cnt + 1;
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end
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end
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//-------------------------------------------------------------------------------
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// Initial part pipeline tracelog
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//-------------------------------------------------------------------------------
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`ifdef SCR1_TRACE_LOG_EN
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// Files opening and writing initial header
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initial begin
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$timeformat(-9, 0, " ns", 10);
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#1 hart.hextoa(soc2pipe_fuse_mhartid_i);
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trace_fhandler_core = $fopen({"tracelog_core_", hart, ".log"}, "w");
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// Writing initial header
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$fwrite(trace_fhandler_core, "# RTL_ID %h\n", SCR1_CSR_MIMPID);
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$fwrite(trace_fhandler_core, "#\n");
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// $fwrite(trace_fhandler_core, "# R - return from trap:\n");
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// $fwrite(trace_fhandler_core, "# 1 - MRET\n");
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// $fwrite(trace_fhandler_core, "# 0 - no return\n");
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$fwrite(trace_fhandler_core, "# Events:\n");
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$fwrite(trace_fhandler_core, "# N - no event\n");
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$fwrite(trace_fhandler_core, "# E - exception\n");
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$fwrite(trace_fhandler_core, "# I - interrupt\n");
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$fwrite(trace_fhandler_core, "# W - wakeup\n");
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end
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// Core reset logging and header printing
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always @(posedge rst_n) begin
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$fwrite(trace_fhandler_core, "# =====================================================================================\n");
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`ifndef VERILATOR
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$fwrite(trace_fhandler_core, "# %16d ns : Core Reset\n", $time());
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`else
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$fwrite(trace_fhandler_core, "# : Core Reset\n");
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`endif
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$fwrite(trace_fhandler_core, "# =====================================================================================\n");
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$fwrite(trace_fhandler_core, "# Test: %s\n", test_name);
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$fwrite(trace_fhandler_core, "# Time ");
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// $fwrite(trace_fhandler_core, " R ");
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$fwrite(trace_fhandler_core, " Ev ");
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$fwrite(trace_fhandler_core, " Curr_PC ");
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$fwrite(trace_fhandler_core, " Instr ");
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$fwrite(trace_fhandler_core, " Next_PC ");
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$fwrite(trace_fhandler_core, " Reg ");
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$fwrite(trace_fhandler_core, " Value ");
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$fwrite(trace_fhandler_core, "\n");
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$fwrite(trace_fhandler_core, "# =====================================================================================\n");
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end
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//-------------------------------------------------------------------------------
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// Common trace part
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//-------------------------------------------------------------------------------
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assign trace_flag = 1'b1;
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assign trace_update = (exu2trace_update_pc_en_i | mprf2trace_wr_en_i) & trace_flag;
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always_ff @(posedge clk) begin
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if (~rst_n) begin
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current_time <= 0;
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event_type <= "N";
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trace_pc <= 'x;
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trace_npc <= 'x;
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trace_instr <= 'x;
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trace_update_r <= 1'b0;
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mprf_up <= '0;
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mprf_addr <= '0;
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mprf_wdata <= '0;
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end else begin
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trace_update_r <= trace_update;
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if (trace_update) begin
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`ifdef VERILATOR
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current_time <= time_cnt;
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`else
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current_time <= $time();
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`endif
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trace_pc <= trace_npc;
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trace_npc <= exu2trace_update_pc_i;
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trace_instr <= ifu2trace_instr_i;
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if (csr2trace_e_exc_i) begin
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// Exception
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event_type <= "E";
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end
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else if (csr2trace_e_irq_i) begin
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// IRQ
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event_type <= "I";
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end
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else if (pipe2trace_e_wake_i) begin
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// Wake
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event_type <= "W";
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end
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else begin
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// No event
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event_type <= "N";
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end
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end
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// Write log signals
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mprf_up <= mprf2trace_wr_en_i;
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mprf_addr <= mprf2trace_wr_en_i ? mprf2trace_wr_addr_i : 'x;
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mprf_wdata <= mprf2trace_wr_en_i ? mprf2trace_wr_data_i : 'x;
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end
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end
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//-------------------------------------------------------------------------------
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// Core MPRF logging
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//-------------------------------------------------------------------------------
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always_ff @(negedge rst_n, posedge clk) begin
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if (~rst_n) begin
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end else begin
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if (trace_update_r) begin
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trace_write_common();
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case (event_type)
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"W" : begin
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// Wakeup
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if (csr_trace1.mip & csr_trace1.mie) begin
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$fwrite(trace_fhandler_core, " mip %08x\n", csr_trace1.mip );
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trace_write_common();
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$fwrite(trace_fhandler_core, " mie %08x", csr_trace1.mie );
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end
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end
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"N" : begin
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// Regular
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if (mprf_up && mprf_addr != 0) begin
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// $fwrite(trace_fhandler_core, " x%2d %08x", mprf_addr, mprf_wdata);
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trace_write_int_walias();
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$fwrite(trace_fhandler_core, " %08x", mprf_wdata);
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end else begin
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$fwrite(trace_fhandler_core, " --- --------");
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end
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|
end
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"R" : begin
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// MRET
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$fwrite(trace_fhandler_core, " mstatus %08x", csr_trace1.mstatus);
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|
end
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|
"E", "I": begin
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// IRQ/Exception
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|
$fwrite(trace_fhandler_core, " mstatus %08x\n", csr_trace1.mstatus);
|
|
trace_write_common();
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|
$fwrite(trace_fhandler_core, " mepc %08x\n", csr_trace1.mepc);
|
|
trace_write_common();
|
|
$fwrite(trace_fhandler_core, " mcause %08x\n", csr_trace1.mcause);
|
|
trace_write_common();
|
|
$fwrite(trace_fhandler_core, " mtval %08x", csr_trace1.mtval);
|
|
end
|
|
default : begin
|
|
$fwrite(trace_fhandler_core, "\n");
|
|
end
|
|
endcase
|
|
$fwrite(trace_fhandler_core, "\n");
|
|
end
|
|
end
|
|
end
|
|
|
|
//-------------------------------------------------------------------------------
|
|
// Core CSR logging
|
|
//-------------------------------------------------------------------------------
|
|
|
|
always_comb begin
|
|
csr_trace1.mtvec = {csr2trace_mtvec_base_i, 4'd0, 2'(csr2trace_mtvec_mode_i)};
|
|
csr_trace1.mepc =
|
|
`ifdef SCR1_RVC_EXT
|
|
{csr2trace_mepc_i, 1'b0};
|
|
`else // SCR1_RVC_EXT
|
|
{csr2trace_mepc_i, 2'b00};
|
|
`endif // SCR1_RVC_EXT
|
|
csr_trace1.mcause = {csr2trace_mcause_irq_i, type_scr1_csr_mcause_ec_v'(csr2trace_mcause_ec_i)};
|
|
csr_trace1.mtval = csr2trace_mtval_i;
|
|
|
|
csr_trace1.mstatus = '0;
|
|
csr_trace1.mie = '0;
|
|
csr_trace1.mip = '0;
|
|
|
|
csr_trace1.mstatus[SCR1_CSR_MSTATUS_MIE_OFFSET] = csr2trace_mstatus_mie_i;
|
|
csr_trace1.mstatus[SCR1_CSR_MSTATUS_MPIE_OFFSET] = csr2trace_mstatus_mpie_i;
|
|
csr_trace1.mstatus[SCR1_CSR_MSTATUS_MPP_OFFSET+1:SCR1_CSR_MSTATUS_MPP_OFFSET] = SCR1_CSR_MSTATUS_MPP;
|
|
csr_trace1.mie[SCR1_CSR_MIE_MSIE_OFFSET] = csr2trace_mie_msie_i;
|
|
csr_trace1.mie[SCR1_CSR_MIE_MTIE_OFFSET] = csr2trace_mie_mtie_i;
|
|
csr_trace1.mie[SCR1_CSR_MIE_MEIE_OFFSET] = csr2trace_mie_meie_i;
|
|
csr_trace1.mip[SCR1_CSR_MIE_MSIE_OFFSET] = csr2trace_mip_msip_i;
|
|
csr_trace1.mip[SCR1_CSR_MIE_MTIE_OFFSET] = csr2trace_mip_mtip_i;
|
|
csr_trace1.mip[SCR1_CSR_MIE_MEIE_OFFSET] = csr2trace_mip_meip_i;
|
|
end
|
|
|
|
`endif // SCR1_TRACE_LOG_EN
|
|
|
|
endmodule : scr1_tracelog
|
|
|
|
`endif // SCR1_TRGT_SIMULATION
|