514 lines
21 KiB
Systemverilog
514 lines
21 KiB
Systemverilog
/// Copyright by Syntacore LLC © 2016-2021. See LICENSE for details
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/// @file <scr1_top_ahb.sv>
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/// @brief SCR1 AHB top
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///
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`include "scr1_arch_description.svh"
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`include "scr1_memif.svh"
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`include "scr1_ahb.svh"
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`ifdef SCR1_IPIC_EN
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`include "scr1_ipic.svh"
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`endif // SCR1_IPIC_EN
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`ifdef SCR1_TCM_EN
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`define SCR1_IMEM_ROUTER_EN
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`endif // SCR1_TCM_EN
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module scr1_top_ahb (
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// Control
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input logic pwrup_rst_n, // Power-Up Reset
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input logic rst_n, // Regular Reset signal
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input logic cpu_rst_n, // CPU Reset (Core Reset)
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input logic test_mode, // Test mode
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input logic test_rst_n, // Test mode's reset
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input logic clk, // System clock
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input logic rtc_clk, // Real-time clock
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`ifdef SCR1_DBG_EN
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output logic sys_rst_n_o, // External System Reset output
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// (for the processor cluster's components or
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// external SOC (could be useful in small
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// SCR-core-centric SOCs))
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output logic sys_rdc_qlfy_o, // System-to-External SOC Reset Domain Crossing Qualifier
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`endif // SCR1_DBG_EN
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// Fuses
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input logic [`SCR1_XLEN-1:0] fuse_mhartid, // Hart ID
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`ifdef SCR1_DBG_EN
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input logic [31:0] fuse_idcode, // TAPC IDCODE
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`endif // SCR1_DBG_EN
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// IRQ
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`ifdef SCR1_IPIC_EN
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input logic [SCR1_IRQ_LINES_NUM-1:0] irq_lines, // IRQ lines to IPIC
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`else // SCR1_IPIC_EN
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input logic ext_irq, // External IRQ input
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`endif // SCR1_IPIC_EN
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input logic soft_irq, // Software IRQ input
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`ifdef SCR1_DBG_EN
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// -- JTAG I/F
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input logic trst_n,
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input logic tck,
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input logic tms,
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input logic tdi,
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output logic tdo,
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output logic tdo_en,
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`endif // SCR1_DBG_EN
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// Instruction Memory Interface
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output logic [3:0] imem_hprot,
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output logic [2:0] imem_hburst,
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output logic [2:0] imem_hsize,
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output logic [1:0] imem_htrans,
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output logic imem_hmastlock,
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output logic [SCR1_AHB_WIDTH-1:0] imem_haddr,
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input logic imem_hready,
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input logic [SCR1_AHB_WIDTH-1:0] imem_hrdata,
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input logic imem_hresp,
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// Data Memory Interface
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output logic [3:0] dmem_hprot,
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output logic [2:0] dmem_hburst,
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output logic [2:0] dmem_hsize,
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output logic [1:0] dmem_htrans,
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output logic dmem_hmastlock,
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output logic [SCR1_AHB_WIDTH-1:0] dmem_haddr,
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output logic dmem_hwrite,
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output logic [SCR1_AHB_WIDTH-1:0] dmem_hwdata,
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input logic dmem_hready,
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input logic [SCR1_AHB_WIDTH-1:0] dmem_hrdata,
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input logic dmem_hresp
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);
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//-------------------------------------------------------------------------------
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// Local parameters
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//-------------------------------------------------------------------------------
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localparam int unsigned SCR1_CLUSTER_TOP_RST_SYNC_STAGES_NUM = 2;
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//-------------------------------------------------------------------------------
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// Local signal declaration
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//-------------------------------------------------------------------------------
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// Reset logic
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logic pwrup_rst_n_sync;
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logic rst_n_sync;
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logic cpu_rst_n_sync;
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logic core_rst_n_local;
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`ifdef SCR1_DBG_EN
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logic tapc_trst_n;
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`endif // SCR1_DBG_EN
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// Instruction memory interface from core to router
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logic core_imem_req_ack;
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logic core_imem_req;
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type_scr1_mem_cmd_e core_imem_cmd;
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logic [`SCR1_IMEM_AWIDTH-1:0] core_imem_addr;
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logic [`SCR1_IMEM_DWIDTH-1:0] core_imem_rdata;
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type_scr1_mem_resp_e core_imem_resp;
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// Data memory interface from core to router
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logic core_dmem_req_ack;
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logic core_dmem_req;
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type_scr1_mem_cmd_e core_dmem_cmd;
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type_scr1_mem_width_e core_dmem_width;
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logic [`SCR1_DMEM_AWIDTH-1:0] core_dmem_addr;
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logic [`SCR1_DMEM_DWIDTH-1:0] core_dmem_wdata;
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logic [`SCR1_DMEM_DWIDTH-1:0] core_dmem_rdata;
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type_scr1_mem_resp_e core_dmem_resp;
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// Instruction memory interface from router to AHB bridge
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logic ahb_imem_req_ack;
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logic ahb_imem_req;
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type_scr1_mem_cmd_e ahb_imem_cmd;
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logic [`SCR1_IMEM_AWIDTH-1:0] ahb_imem_addr;
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logic [`SCR1_IMEM_DWIDTH-1:0] ahb_imem_rdata;
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type_scr1_mem_resp_e ahb_imem_resp;
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// Data memory interface from router to AHB bridge
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logic ahb_dmem_req_ack;
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logic ahb_dmem_req;
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type_scr1_mem_cmd_e ahb_dmem_cmd;
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type_scr1_mem_width_e ahb_dmem_width;
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logic [`SCR1_DMEM_AWIDTH-1:0] ahb_dmem_addr;
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logic [`SCR1_DMEM_DWIDTH-1:0] ahb_dmem_wdata;
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logic [`SCR1_DMEM_DWIDTH-1:0] ahb_dmem_rdata;
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type_scr1_mem_resp_e ahb_dmem_resp;
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`ifdef SCR1_TCM_EN
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// Instruction memory interface from router to TCM
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logic tcm_imem_req_ack;
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logic tcm_imem_req;
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type_scr1_mem_cmd_e tcm_imem_cmd;
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logic [`SCR1_IMEM_AWIDTH-1:0] tcm_imem_addr;
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logic [`SCR1_IMEM_DWIDTH-1:0] tcm_imem_rdata;
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type_scr1_mem_resp_e tcm_imem_resp;
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// Data memory interface from router to TCM
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logic tcm_dmem_req_ack;
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logic tcm_dmem_req;
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type_scr1_mem_cmd_e tcm_dmem_cmd;
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type_scr1_mem_width_e tcm_dmem_width;
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logic [`SCR1_DMEM_AWIDTH-1:0] tcm_dmem_addr;
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logic [`SCR1_DMEM_DWIDTH-1:0] tcm_dmem_wdata;
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logic [`SCR1_DMEM_DWIDTH-1:0] tcm_dmem_rdata;
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type_scr1_mem_resp_e tcm_dmem_resp;
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`endif // SCR1_TCM_EN
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// Data memory interface from router to memory-mapped timer
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logic timer_dmem_req_ack;
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logic timer_dmem_req;
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type_scr1_mem_cmd_e timer_dmem_cmd;
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type_scr1_mem_width_e timer_dmem_width;
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logic [`SCR1_DMEM_AWIDTH-1:0] timer_dmem_addr;
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logic [`SCR1_DMEM_DWIDTH-1:0] timer_dmem_wdata;
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logic [`SCR1_DMEM_DWIDTH-1:0] timer_dmem_rdata;
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type_scr1_mem_resp_e timer_dmem_resp;
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logic timer_irq;
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logic [63:0] timer_val;
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//-------------------------------------------------------------------------------
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// Reset logic
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//-------------------------------------------------------------------------------
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// Power-Up Reset synchronizer
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scr1_reset_sync_cell #(
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.STAGES_AMOUNT (SCR1_CLUSTER_TOP_RST_SYNC_STAGES_NUM)
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) i_pwrup_rstn_reset_sync (
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.rst_n (pwrup_rst_n ),
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.clk (clk ),
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.test_rst_n (test_rst_n ),
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.test_mode (test_mode ),
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.rst_n_in (1'b1 ),
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.rst_n_out (pwrup_rst_n_sync)
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);
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// Regular Reset synchronizer
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scr1_reset_sync_cell #(
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.STAGES_AMOUNT (SCR1_CLUSTER_TOP_RST_SYNC_STAGES_NUM)
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) i_rstn_reset_sync (
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.rst_n (pwrup_rst_n ),
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.clk (clk ),
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.test_rst_n (test_rst_n ),
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.test_mode (test_mode ),
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.rst_n_in (rst_n ),
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.rst_n_out (rst_n_sync )
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);
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// CPU Reset synchronizer
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scr1_reset_sync_cell #(
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.STAGES_AMOUNT (SCR1_CLUSTER_TOP_RST_SYNC_STAGES_NUM)
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) i_cpu_rstn_reset_sync (
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.rst_n (pwrup_rst_n ),
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.clk (clk ),
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.test_rst_n (test_rst_n ),
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.test_mode (test_mode ),
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.rst_n_in (cpu_rst_n ),
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.rst_n_out (cpu_rst_n_sync )
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);
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`ifdef SCR1_DBG_EN
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// TAPC Reset
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scr1_reset_and2_cell i_tapc_rstn_and2_cell (
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.rst_n_in ({trst_n, pwrup_rst_n}),
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.test_rst_n (test_rst_n ),
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.test_mode (test_mode ),
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.rst_n_out (tapc_trst_n )
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);
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`endif // SCR1_DBG_EN
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//-------------------------------------------------------------------------------
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// SCR1 core instance
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//-------------------------------------------------------------------------------
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scr1_core_top i_core_top (
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// Common
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.pwrup_rst_n (pwrup_rst_n_sync ),
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.rst_n (rst_n_sync ),
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.cpu_rst_n (cpu_rst_n_sync ),
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.test_mode (test_mode ),
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.test_rst_n (test_rst_n ),
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.clk (clk ),
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.core_rst_n_o (core_rst_n_local ),
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.core_rdc_qlfy_o ( ),
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`ifdef SCR1_DBG_EN
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.sys_rst_n_o (sys_rst_n_o ),
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.sys_rdc_qlfy_o (sys_rdc_qlfy_o ),
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`endif // SCR1_DBG_EN
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// Fuses
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.core_fuse_mhartid_i (fuse_mhartid ),
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`ifdef SCR1_DBG_EN
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.tapc_fuse_idcode_i (fuse_idcode ),
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`endif // SCR1_DBG_EN
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// IRQ
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`ifdef SCR1_IPIC_EN
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.core_irq_lines_i (irq_lines ),
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`else // SCR1_IPIC_EN
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.core_irq_ext_i (ext_irq ),
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`endif // SCR1_IPIC_EN
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.core_irq_soft_i (soft_irq ),
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.core_irq_mtimer_i (timer_irq ),
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// Memory-mapped external timer
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.core_mtimer_val_i (timer_val ),
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`ifdef SCR1_DBG_EN
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// Debug interface
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.tapc_trst_n (tapc_trst_n ),
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.tapc_tck (tck ),
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.tapc_tms (tms ),
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.tapc_tdi (tdi ),
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.tapc_tdo (tdo ),
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.tapc_tdo_en (tdo_en ),
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`endif // SCR1_DBG_EN
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// Instruction memory interface
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.imem2core_req_ack_i (core_imem_req_ack),
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.core2imem_req_o (core_imem_req ),
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.core2imem_cmd_o (core_imem_cmd ),
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.core2imem_addr_o (core_imem_addr ),
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.imem2core_rdata_i (core_imem_rdata ),
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.imem2core_resp_i (core_imem_resp ),
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// Data memory interface
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.dmem2core_req_ack_i (core_dmem_req_ack),
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.core2dmem_req_o (core_dmem_req ),
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.core2dmem_cmd_o (core_dmem_cmd ),
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.core2dmem_width_o (core_dmem_width ),
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.core2dmem_addr_o (core_dmem_addr ),
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.core2dmem_wdata_o (core_dmem_wdata ),
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.dmem2core_rdata_i (core_dmem_rdata ),
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.dmem2core_resp_i (core_dmem_resp )
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);
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`ifdef SCR1_TCM_EN
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//-------------------------------------------------------------------------------
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// TCM instance
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//-------------------------------------------------------------------------------
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scr1_tcm #(
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.SCR1_TCM_SIZE (`SCR1_DMEM_AWIDTH'(~SCR1_TCM_ADDR_MASK + 1'b1))
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) i_tcm (
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.clk (clk ),
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.rst_n (core_rst_n_local),
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// Instruction interface to TCM
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.imem_req_ack (tcm_imem_req_ack),
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.imem_req (tcm_imem_req ),
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.imem_addr (tcm_imem_addr ),
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.imem_rdata (tcm_imem_rdata ),
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.imem_resp (tcm_imem_resp ),
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// Data interface to TCM
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.dmem_req_ack (tcm_dmem_req_ack),
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.dmem_req (tcm_dmem_req ),
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.dmem_cmd (tcm_dmem_cmd ),
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.dmem_width (tcm_dmem_width ),
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.dmem_addr (tcm_dmem_addr ),
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.dmem_wdata (tcm_dmem_wdata ),
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.dmem_rdata (tcm_dmem_rdata ),
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.dmem_resp (tcm_dmem_resp )
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);
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`endif // SCR1_TCM_EN
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//-------------------------------------------------------------------------------
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// Memory-mapped timer instance
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//-------------------------------------------------------------------------------
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scr1_timer i_timer (
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// Common
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.rst_n (core_rst_n_local ),
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.clk (clk ),
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.rtc_clk (rtc_clk ),
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// Memory interface
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.dmem_req (timer_dmem_req ),
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.dmem_cmd (timer_dmem_cmd ),
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.dmem_width (timer_dmem_width ),
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.dmem_addr (timer_dmem_addr ),
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.dmem_wdata (timer_dmem_wdata ),
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.dmem_req_ack (timer_dmem_req_ack),
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.dmem_rdata (timer_dmem_rdata ),
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.dmem_resp (timer_dmem_resp ),
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// Timer interface
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.timer_val (timer_val ),
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.timer_irq (timer_irq )
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);
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`ifdef SCR1_IMEM_ROUTER_EN
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//-------------------------------------------------------------------------------
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// Instruction memory router
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//-------------------------------------------------------------------------------
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scr1_imem_router #(
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`ifdef SCR1_TCM_EN
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.SCR1_ADDR_MASK (SCR1_TCM_ADDR_MASK),
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.SCR1_ADDR_PATTERN (SCR1_TCM_ADDR_PATTERN)
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`endif // SCR1_TCM_EN
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) i_imem_router (
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.rst_n (core_rst_n_local ),
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.clk (clk ),
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// Interface to core
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.imem_req_ack (core_imem_req_ack),
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.imem_req (core_imem_req ),
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.imem_cmd (core_imem_cmd ),
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.imem_addr (core_imem_addr ),
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.imem_rdata (core_imem_rdata ),
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.imem_resp (core_imem_resp ),
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// Interface to AHB bridge
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.port0_req_ack (ahb_imem_req_ack ),
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.port0_req (ahb_imem_req ),
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.port0_cmd (ahb_imem_cmd ),
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.port0_addr (ahb_imem_addr ),
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.port0_rdata (ahb_imem_rdata ),
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.port0_resp (ahb_imem_resp ),
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`ifdef SCR1_TCM_EN
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// Interface to TCM
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.port1_req_ack (tcm_imem_req_ack ),
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.port1_req (tcm_imem_req ),
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.port1_cmd (tcm_imem_cmd ),
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.port1_addr (tcm_imem_addr ),
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.port1_rdata (tcm_imem_rdata ),
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.port1_resp (tcm_imem_resp )
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`endif // SCR1_TCM_EN
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);
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`else // SCR1_IMEM_ROUTER_EN
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assign ahb_imem_req = core_imem_req;
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assign ahb_imem_cmd = core_imem_cmd;
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assign ahb_imem_addr = core_imem_addr;
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assign core_imem_req_ack = ahb_imem_req_ack;
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assign core_imem_resp = ahb_imem_resp;
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assign core_imem_rdata = ahb_imem_rdata;
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`endif // SCR1_IMEM_ROUTER_EN
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//-------------------------------------------------------------------------------
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// Data memory router
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//-------------------------------------------------------------------------------
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scr1_dmem_router #(
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`ifdef SCR1_TCM_EN
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.SCR1_PORT1_ADDR_MASK (SCR1_TCM_ADDR_MASK),
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.SCR1_PORT1_ADDR_PATTERN (SCR1_TCM_ADDR_PATTERN),
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`else // SCR1_TCM_EN
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.SCR1_PORT1_ADDR_MASK (32'h00000000),
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.SCR1_PORT1_ADDR_PATTERN (32'hFFFFFFFF),
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`endif // SCR1_TCM_EN
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.SCR1_PORT2_ADDR_MASK (SCR1_TIMER_ADDR_MASK),
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.SCR1_PORT2_ADDR_PATTERN (SCR1_TIMER_ADDR_PATTERN)
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) i_dmem_router (
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.rst_n (core_rst_n_local ),
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.clk (clk ),
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// Interface to core
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.dmem_req_ack (core_dmem_req_ack ),
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.dmem_req (core_dmem_req ),
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.dmem_cmd (core_dmem_cmd ),
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.dmem_width (core_dmem_width ),
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.dmem_addr (core_dmem_addr ),
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.dmem_wdata (core_dmem_wdata ),
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.dmem_rdata (core_dmem_rdata ),
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.dmem_resp (core_dmem_resp ),
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`ifdef SCR1_TCM_EN
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// Interface to TCM
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.port1_req_ack (tcm_dmem_req_ack ),
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.port1_req (tcm_dmem_req ),
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.port1_cmd (tcm_dmem_cmd ),
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.port1_width (tcm_dmem_width ),
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.port1_addr (tcm_dmem_addr ),
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.port1_wdata (tcm_dmem_wdata ),
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.port1_rdata (tcm_dmem_rdata ),
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.port1_resp (tcm_dmem_resp ),
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`else // SCR1_TCM_EN
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.port1_req_ack (1'b0),
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.port1_req ( ),
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.port1_cmd ( ),
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.port1_width ( ),
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.port1_addr ( ),
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.port1_wdata ( ),
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.port1_rdata ('0 ),
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.port1_resp (SCR1_MEM_RESP_RDY_ER),
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`endif // SCR1_TCM_EN
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// Interface to memory-mapped timer
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.port2_req_ack (timer_dmem_req_ack ),
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.port2_req (timer_dmem_req ),
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.port2_cmd (timer_dmem_cmd ),
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.port2_width (timer_dmem_width ),
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|
.port2_addr (timer_dmem_addr ),
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|
.port2_wdata (timer_dmem_wdata ),
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|
.port2_rdata (timer_dmem_rdata ),
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|
.port2_resp (timer_dmem_resp ),
|
|
// Interface to AHB bridge
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|
.port0_req_ack (ahb_dmem_req_ack ),
|
|
.port0_req (ahb_dmem_req ),
|
|
.port0_cmd (ahb_dmem_cmd ),
|
|
.port0_width (ahb_dmem_width ),
|
|
.port0_addr (ahb_dmem_addr ),
|
|
.port0_wdata (ahb_dmem_wdata ),
|
|
.port0_rdata (ahb_dmem_rdata ),
|
|
.port0_resp (ahb_dmem_resp )
|
|
);
|
|
|
|
|
|
//-------------------------------------------------------------------------------
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// Instruction memory AHB bridge
|
|
//-------------------------------------------------------------------------------
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scr1_imem_ahb i_imem_ahb (
|
|
.rst_n (core_rst_n_local ),
|
|
.clk (clk ),
|
|
// Interface to imem router
|
|
.imem_req_ack (ahb_imem_req_ack ),
|
|
.imem_req (ahb_imem_req ),
|
|
.imem_addr (ahb_imem_addr ),
|
|
.imem_rdata (ahb_imem_rdata ),
|
|
.imem_resp (ahb_imem_resp ),
|
|
// AHB interface
|
|
.hprot (imem_hprot ),
|
|
.hburst (imem_hburst ),
|
|
.hsize (imem_hsize ),
|
|
.htrans (imem_htrans ),
|
|
.hmastlock (imem_hmastlock ),
|
|
.haddr (imem_haddr ),
|
|
.hready (imem_hready ),
|
|
.hrdata (imem_hrdata ),
|
|
.hresp (imem_hresp )
|
|
);
|
|
|
|
|
|
//-------------------------------------------------------------------------------
|
|
// Data memory AHB bridge
|
|
//-------------------------------------------------------------------------------
|
|
scr1_dmem_ahb i_dmem_ahb (
|
|
.rst_n (core_rst_n_local ),
|
|
.clk (clk ),
|
|
// Interface to dmem router
|
|
.dmem_req_ack (ahb_dmem_req_ack ),
|
|
.dmem_req (ahb_dmem_req ),
|
|
.dmem_cmd (ahb_dmem_cmd ),
|
|
.dmem_width (ahb_dmem_width ),
|
|
.dmem_addr (ahb_dmem_addr ),
|
|
.dmem_wdata (ahb_dmem_wdata ),
|
|
.dmem_rdata (ahb_dmem_rdata ),
|
|
.dmem_resp (ahb_dmem_resp ),
|
|
// AHB interface
|
|
.hprot (dmem_hprot ),
|
|
.hburst (dmem_hburst ),
|
|
.hsize (dmem_hsize ),
|
|
.htrans (dmem_htrans ),
|
|
.hmastlock (dmem_hmastlock ),
|
|
.haddr (dmem_haddr ),
|
|
.hwrite (dmem_hwrite ),
|
|
.hwdata (dmem_hwdata ),
|
|
.hready (dmem_hready ),
|
|
.hrdata (dmem_hrdata ),
|
|
.hresp (dmem_hresp )
|
|
);
|
|
|
|
endmodule : scr1_top_ahb
|
|
|
|
|