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compare: riscv_school:main
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2 Commits
0f3384e157 ... main

Author SHA1 Message Date
Mikhail Yenuchenko
b3e5f395a1 Update RUN_PAR.tcl 2026-01-21 16:42:58 +03:00
Mikhail Yenuchenko
12b848a74c Update FLOW_PAR.tcl 2026-01-21 16:42:55 +03:00
2 changed files with 2 additions and 2 deletions
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2
scripts/scripts_PaR/FLOW_PAR.tcl
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@@ -13,7 +13,7 @@ if {$PaR_INIT eq "TRUE"} {
set init_verilog ${NETLIST_PATH}/${NETLIST_TOP_NAME}; # SYN netlist file
set init_mmmc_file ${PAR_MMMC_FILE}; # Techmological file for multi-mode multi-corner PaR
set init_io_file ${PAR_NETLIST_TOP_PORT_FILE}; # File with location of the TOP level ports on the floorplan
#set init_io_file ${PAR_NETLIST_TOP_PORT_FILE}; # File with location of the TOP level ports on the floorplan
init_design
}

2
scripts/scripts_PaR/RUN_PAR.tcl
View File

@@ -28,7 +28,7 @@ set PAR_INIT_LEF_FILESET "/Cadence/Libs/X_FAB/XKIT/xt018/cadence/v7_0/techLEF/v7
set PAR_REPORTS_FOLDER "../reports/reports_PaR"; # Reports folder
set PAR_RESULTS_FOLDER "../results/results_PaR"; # Results folder
set FLOORPLAN_DIMENSIONS {9000 9000}; # FP chip area
set FLOORPLAN_DIMENSIONS {500 500}; # FP chip area
set FLOORPLAN_MARGINS {50 50 50 50}; #FP chip margins
### ================= END of USER SETTINGS =============