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This commit is contained in:
Mikhail Yenuchenko
2026-01-20 16:23:00 +03:00
commit c8ab0ca4f7
107 changed files with 285173 additions and 0 deletions
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/// Copyright by Syntacore LLC © 2016-2021. See LICENSE for details
/// @file <scr1_ahb.svh>
/// @brief AHB header file
///
`ifndef SCR1_AHB_SVH
`define SCR1_AHB_SVH
`include "scr1_arch_description.svh"
parameter SCR1_AHB_WIDTH = 32;
// Encoding for HTRANS signal
parameter logic [1:0] SCR1_HTRANS_IDLE = 2'b00;
parameter logic [1:0] SCR1_HTRANS_NONSEQ = 2'b10;
`ifdef SCR1_XPROP_EN
parameter logic [1:0] SCR1_HTRANS_ERR = 'x;
`else // SCR1_XPROP_EN
parameter logic [1:0] SCR1_HTRANS_ERR = '0;
`endif // SCR1_XPROP_EN
// Encoding for HBURST signal
parameter logic [2:0] SCR1_HBURST_SINGLE = 3'b000;
`ifdef SCR1_XPROP_EN
parameter logic [2:0] SCR1_HBURST_ERR = 'x;
`else // SCR1_XPROP_EN
parameter logic [1:0] SCR1_HBURST_ERR = '0;
`endif // SCR1_XPROP_EN
// Encoding for HSIZE signal
parameter logic [2:0] SCR1_HSIZE_8B = 3'b000;
parameter logic [2:0] SCR1_HSIZE_16B = 3'b001;
parameter logic [2:0] SCR1_HSIZE_32B = 3'b010;
`ifdef SCR1_XPROP_EN
parameter logic [2:0] SCR1_HSIZE_ERR = 'x;
`else // SCR1_XPROP_EN
parameter logic [2:0] SCR1_HSIZE_ERR = '0;
`endif // SCR1_XPROP_EN
// Encoding HPROT signal
// HPROT[0] : 0 - instr; 1 - data
// HPROT[1] : 0 - user; 1 - privilege
// HPROT[2] : 0 - not buffer; 1 - buffer
// HPROT[3] : 0 - cacheable; 1 - cacheable
parameter SCR1_HPROT_DATA = 0;
parameter SCR1_HPROT_PRV = 1;
parameter SCR1_HPROT_BUF = 2;
parameter SCR1_HPROT_CACHE = 3;
// Encoding HRESP signal
parameter logic SCR1_HRESP_OKAY = 1'b0;
parameter logic SCR1_HRESP_ERROR = 1'b1;
`ifdef SCR1_XPROP_EN
parameter logic SCR1_HRESP_ERR = 1'bx;
`else // SCR1_XPROP_EN
parameter logic SCR1_HRESP_ERR = 1'b0;
`endif // SCR1_XPROP_EN
`endif // SCR1_AHB_SVH

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/// Copyright by Syntacore LLC © 2016-2021. See LICENSE for details
/// @file <scr1_arch_description.svh>
/// @brief Architecture description file
///
`ifndef SCR1_ARCH_DESCRIPTION_SVH
`define SCR1_ARCH_DESCRIPTION_SVH
//------------------------------------------------------------------------------
// CORE FUNDAMENTAL PARAMETERS
//------------------------------------------------------------------------------
// SCR1 core identifiers
`define SCR1_MIMPID 32'h22011200
`define SCR1_MVENDORID 32'h00000000
// Width of main registers and buses
`define SCR1_XLEN 32
`define SCR1_IMEM_AWIDTH `SCR1_XLEN
`define SCR1_IMEM_DWIDTH `SCR1_XLEN
`define SCR1_DMEM_AWIDTH `SCR1_XLEN
`define SCR1_DMEM_DWIDTH `SCR1_XLEN
// TAP IDCODE
`define SCR1_TAP_IDCODE 'hDEB11001
`ifdef SCR1_ARCH_CUSTOM
//------------------------------------------------------------------------------
// INCLUDE SCR1_ARCH_CUSTOM.SVH
//------------------------------------------------------------------------------
// The external file scr1_arch_custom.svh is used for the open SCR1-SDK project,
// and can also be used for any custom projects.
// The file sets:
// - target platform (FPGA/ASIC), which affects the choice of logical constructs;
// - device build ID;
// - address constants;
// - could enables configuration parameters.
// Possible targets:
// `define SCR1_TRGT_FPGA_INTEL // target platform is Intel FPGAs
// `define SCR1_TRGT_FPGA_INTEL_MAX10 // target platform is Intel MAX 10 FPGAs (used in the SCR1-SDK project)
// `define SCR1_TRGT_FPGA_INTEL_ARRIAV // target platform is Intel Arria V FPGAs (used in the SCR1-SDK project)
// `define SCR1_TRGT_FPGA_XILINX // target platform is Xilinx FPGAs (used in the SCR1-SDK project)
// `define SCR1_TRGT_ASIC // target platform is ASIC
// `define SCR1_TRGT_SIMULATION // target is simulation (enable simulation code)
`include "scr1_arch_custom.svh"
`endif // SCR1_ARCH_CUSTOM
//------------------------------------------------------------------------------
// RECOMMENDED CORE ARCHITECTURE CONFIGURATIONS
//------------------------------------------------------------------------------
// Uncomment one of these defines to set the recommended configuration:
//`define SCR1_CFG_RV32IMC_MAX
//`define SCR1_CFG_RV32IC_BASE
//`define SCR1_CFG_RV32EC_MIN
// If all defines are commented, custom configuration will be used (see below)
//------------------------------------------------------------------------------
// READ-ONLY: settings for recommended configurations
`ifdef SCR1_CFG_RV32IMC_MAX
`define SCR1_RVI_EXT
`define SCR1_RVM_EXT
`define SCR1_RVC_EXT
parameter int unsigned SCR1_MTVEC_BASE_WR_BITS = 26;
`define SCR1_MTVEC_MODE_EN
`define SCR1_FAST_MUL
`define SCR1_MPRF_RST_EN
`define SCR1_MCOUNTEN_EN
`define SCR1_DBG_EN
`define SCR1_TDU_EN
parameter int unsigned SCR1_TDU_TRIG_NUM = 4;
`define SCR1_TDU_ICOUNT_EN
`define SCR1_IPIC_EN
`define SCR1_IPIC_SYNC_EN
`define SCR1_TCM_EN
`elsif SCR1_CFG_RV32IC_BASE
`define SCR1_RVI_EXT
`define SCR1_RVC_EXT
parameter int unsigned SCR1_MTVEC_BASE_WR_BITS = 16;
`define SCR1_MTVEC_MODE_EN
`define SCR1_NO_DEC_STAGE
`define SCR1_MPRF_RST_EN
`define SCR1_MCOUNTEN_EN
`define SCR1_DBG_EN
`define SCR1_TDU_EN
parameter int unsigned SCR1_TDU_TRIG_NUM = 2;
`define SCR1_TDU_ICOUNT_EN
`define SCR1_IPIC_EN
`define SCR1_IPIC_SYNC_EN
`define SCR1_TCM_EN
`elsif SCR1_CFG_RV32EC_MIN
`define SCR1_RVE_EXT
`define SCR1_RVC_EXT
parameter int unsigned SCR1_MTVEC_BASE_WR_BITS = 0;
`define SCR1_NO_DEC_STAGE
`define SCR1_NO_EXE_STAGE
`define SCR1_TCM_EN
`else // begin custom configuration section
//------------------------------------------------------------------------------
// CUSTOM CORE ARCHITECTURE CONFIGURATION
//------------------------------------------------------------------------------
// To fine-tune custom configuration, you can change the values in this section.
// Make sure that the defines of the recommended configurations are commented,
// otherwise this section will be inactive.
// RISC-V ISA options
//`define SCR1_RVE_EXT // enable RV32E base integer instruction set, otherwise RV32I will be used
`define SCR1_RVM_EXT // enable standard extension "M" for integer hardware multiplier and divider
`define SCR1_RVC_EXT // enable standard extension "C" for compressed instructions
parameter int unsigned SCR1_MTVEC_BASE_WR_BITS = 26; // number of writable high-order bits in MTVEC.base field
// legal values are 0 to 26
// read-only bits are hardwired to reset value
`define SCR1_MTVEC_MODE_EN // enable writable MTVEC.mode field to allow vectored irq mode, otherwise only direct mode is possible
`ifndef SCR1_RVE_EXT
`define SCR1_RVI_EXT // RV32E base integer instruction set if SCR1_RVE_EXT is not enabled
`endif // ~SCR1_RVE_EXT
// Core pipeline options (power-performance-area optimization)
`define SCR1_NO_DEC_STAGE // disable register between IFU and IDU
`define SCR1_NO_EXE_STAGE // disable register between IDU and EXU
`define SCR1_NEW_PC_REG // enable register in IFU for New_PC value
`define SCR1_FAST_MUL // enable fast one-cycle multiplication, otherwise multiplication takes 32 cycles
`define SCR1_CLKCTRL_EN // enable global clock gating
`define SCR1_MPRF_RST_EN // enable reset for MPRF
`define SCR1_MCOUNTEN_EN // enable custom MCOUNTEN CSR for counter control
// Uncore options
`define SCR1_DBG_EN // enable Debug Subsystem (TAPC, DM, SCU, HDU)
`define SCR1_TDU_EN // enable Trigger Debug Unit (hardware breakpoints)
parameter int unsigned SCR1_TDU_TRIG_NUM = 2; // number of hardware triggers
`define SCR1_TDU_ICOUNT_EN // enable hardware triggers on instruction counter
`define SCR1_IPIC_EN // enable Integrated Programmable Interrupt Controller
`define SCR1_IPIC_SYNC_EN // enable IPIC synchronizer
`define SCR1_TCM_EN // enable Tightly-Coupled Memory
`endif // end custom configuration section
//------------------------------------------------------------------------------
// CORE INTEGRATION OPTIONS
//------------------------------------------------------------------------------
// Bypasses on AXI/AHB bridge I/O
`define SCR1_IMEM_AHB_IN_BP // bypass instruction memory AHB bridge input register
`define SCR1_IMEM_AHB_OUT_BP // bypass instruction memory AHB bridge output register
`define SCR1_DMEM_AHB_IN_BP // bypass data memory AHB bridge input register
`define SCR1_DMEM_AHB_OUT_BP // bypass data memory AHB bridge output register
`define SCR1_IMEM_AXI_REQ_BP // bypass instruction memory AXI bridge request register
`define SCR1_IMEM_AXI_RESP_BP // bypass instruction memory AXI bridge response register
`define SCR1_DMEM_AXI_REQ_BP // bypass data memory AXI bridge request register
`define SCR1_DMEM_AXI_RESP_BP // bypass data memory AXI bridge response register
`ifndef SCR1_ARCH_CUSTOM
// Default address constants (if scr1_arch_custom.svh is not used)
parameter bit [`SCR1_XLEN-1:0] SCR1_ARCH_RST_VECTOR = 'h200; // Reset vector value (start address after reset)
parameter bit [`SCR1_XLEN-1:0] SCR1_ARCH_MTVEC_BASE = 'h1C0; // MTVEC.base field reset value, or constant value for MTVEC.base bits that are hardwired
parameter bit [`SCR1_DMEM_AWIDTH-1:0] SCR1_TCM_ADDR_MASK = 'hFFFF0000; // TCM mask and size; size in bytes is two's complement of the mask value
parameter bit [`SCR1_DMEM_AWIDTH-1:0] SCR1_TCM_ADDR_PATTERN = 'h00480000; // TCM address match pattern
parameter bit [`SCR1_DMEM_AWIDTH-1:0] SCR1_TIMER_ADDR_MASK = 'hFFFFFFE0; // Timer mask
parameter bit [`SCR1_DMEM_AWIDTH-1:0] SCR1_TIMER_ADDR_PATTERN = 'h00490000; // Timer address match pattern
// Device build ID
`define SCR1_ARCH_BUILD_ID `SCR1_MIMPID
`endif // SCR1_ARCH_CUSTOM
//------------------------------------------------------------------------------
// TARGET-SPECIFIC OPTIONS
//------------------------------------------------------------------------------
// RAM-based MPRF can be used for Intel FPGAs only
`ifdef SCR1_TRGT_FPGA_INTEL
`define SCR1_MPRF_RAM // implements MPRF with dedicated RAM blocks
`endif
// EXU_STAGE_BYPASS and MPRF_RST_EN must be disabled for RAM-based MPRF
`ifdef SCR1_MPRF_RAM
`undef SCR1_NO_EXE_STAGE
`undef SCR1_MPRF_RST_EN
`endif
//------------------------------------------------------------------------------
// SIMULATION OPTIONS
//------------------------------------------------------------------------------
//`define SCR1_TRGT_SIMULATION // enable simulation code (automatically defined by root makefile)
//`define SCR1_TRACE_LOG_EN // enable tracelog
//`define SCR1_XPROP_EN // enable X-propagation
// Addresses used in testbench
localparam [`SCR1_XLEN-1:0] SCR1_SIM_EXIT_ADDR = 32'h0000_00F8;
localparam [`SCR1_XLEN-1:0] SCR1_SIM_PRINT_ADDR = 32'hF000_0000;
localparam [`SCR1_XLEN-1:0] SCR1_SIM_EXT_IRQ_ADDR = 32'hF000_0100;
localparam [`SCR1_XLEN-1:0] SCR1_SIM_SOFT_IRQ_ADDR = 32'hF000_0200;
`endif // SCR1_ARCH_DESCRIPTION_SVH

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/// Copyright by Syntacore LLC © 2016-2021. See LICENSE for details
/// @file <scr1_arch_types.svh>
/// @brief Pipeline types description file
///
`ifndef SCR1_ARCH_TYPES_SVH
`define SCR1_ARCH_TYPES_SVH
`include "scr1_arch_description.svh"
//-------------------------------------------------------------------------------
// MPRF and CSR parameters
//-------------------------------------------------------------------------------
`ifdef SCR1_RVE_EXT
`define SCR1_MPRF_AWIDTH 4
`define SCR1_MPRF_SIZE 16
`else // SCR1_RVE_EXT
`define SCR1_MPRF_AWIDTH 5
`define SCR1_MPRF_SIZE 32
`endif // SCR1_RVE_EXT
typedef logic [`SCR1_XLEN-1:0] type_scr1_mprf_v;
typedef logic [`SCR1_XLEN-1:0] type_scr1_pc_v;
parameter int unsigned SCR1_CSR_ADDR_WIDTH = 12;
parameter int unsigned SCR1_CSR_MTVEC_BASE_ZERO_BITS = 6;
parameter int unsigned SCR1_CSR_MTVEC_BASE_VAL_BITS = `SCR1_XLEN-SCR1_CSR_MTVEC_BASE_ZERO_BITS;
parameter bit [`SCR1_XLEN-1:SCR1_CSR_MTVEC_BASE_ZERO_BITS] SCR1_CSR_MTVEC_BASE_WR_RST_VAL =
SCR1_CSR_MTVEC_BASE_VAL_BITS'(SCR1_ARCH_MTVEC_BASE >> SCR1_CSR_MTVEC_BASE_ZERO_BITS);
parameter int unsigned SCR1_CSR_MTVEC_BASE_RO_BITS = (`SCR1_XLEN-(SCR1_CSR_MTVEC_BASE_ZERO_BITS+SCR1_MTVEC_BASE_WR_BITS));
`define SCR1_MTVAL_ILLEGAL_INSTR_EN
//-------------------------------------------------------------------------------
// Exception and IRQ codes
//-------------------------------------------------------------------------------
parameter int unsigned SCR1_EXC_CODE_WIDTH_E = 4;
// Exceptions
typedef enum logic [SCR1_EXC_CODE_WIDTH_E-1:0] {
SCR1_EXC_CODE_INSTR_MISALIGN = 4'd0, // from EXU
SCR1_EXC_CODE_INSTR_ACCESS_FAULT = 4'd1, // from IFU
SCR1_EXC_CODE_ILLEGAL_INSTR = 4'd2, // from IDU or CSR
SCR1_EXC_CODE_BREAKPOINT = 4'd3, // from IDU or BRKM
SCR1_EXC_CODE_LD_ADDR_MISALIGN = 4'd4, // from LSU
SCR1_EXC_CODE_LD_ACCESS_FAULT = 4'd5, // from LSU
SCR1_EXC_CODE_ST_ADDR_MISALIGN = 4'd6, // from LSU
SCR1_EXC_CODE_ST_ACCESS_FAULT = 4'd7, // from LSU
SCR1_EXC_CODE_ECALL_M = 4'd11 // from IDU
} type_scr1_exc_code_e;
// IRQs, reset
parameter bit [SCR1_EXC_CODE_WIDTH_E-1:0] SCR1_EXC_CODE_IRQ_M_SOFTWARE = 4'd3;
parameter bit [SCR1_EXC_CODE_WIDTH_E-1:0] SCR1_EXC_CODE_IRQ_M_TIMER = 4'd7;
parameter bit [SCR1_EXC_CODE_WIDTH_E-1:0] SCR1_EXC_CODE_IRQ_M_EXTERNAL = 4'd11;
parameter bit [SCR1_EXC_CODE_WIDTH_E-1:0] SCR1_EXC_CODE_RESET = 4'd0;
//-------------------------------------------------------------------------------
// Operand width for BRKM
//-------------------------------------------------------------------------------
typedef enum logic [1:0] {
SCR1_OP_WIDTH_BYTE = 2'b00,
SCR1_OP_WIDTH_HALF = 2'b01,
SCR1_OP_WIDTH_WORD = 2'b10
`ifdef SCR1_XPROP_EN
,
SCR1_OP_WIDTH_ERROR = 'x
`endif // SCR1_XPROP_EN
} type_scr1_op_width_e;
`endif //SCR1_ARCH_TYPES_SVH

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/// Copyright by Syntacore LLC © 2016-2021. See LICENSE for details
/// @file <scr1_csr.svh>
/// @brief CSR mapping/description file
///
`ifndef SCR1_CSR_SVH
`define SCR1_CSR_SVH
`include "scr1_arch_description.svh"
`include "scr1_arch_types.svh"
`include "scr1_ipic.svh"
`ifdef SCR1_RVE_EXT
`define SCR1_CSR_REDUCED_CNT
`endif // SCR1_RVE_EXT
`ifdef SCR1_CSR_REDUCED_CNT
`undef SCR1_MCOUNTEN_EN
`endif // SCR1_CSR_REDUCED_CNT
//-------------------------------------------------------------------------------
// CSR addresses (standard)
//-------------------------------------------------------------------------------
// Machine Information Registers (read-only)
parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_MVENDORID = SCR1_CSR_ADDR_WIDTH'('hF11);
parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_MARCHID = SCR1_CSR_ADDR_WIDTH'('hF12);
parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_MIMPID = SCR1_CSR_ADDR_WIDTH'('hF13);
parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_MHARTID = SCR1_CSR_ADDR_WIDTH'('hF14);
// Machine Trap Setup (read-write)
parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_MSTATUS = SCR1_CSR_ADDR_WIDTH'('h300);
parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_MISA = SCR1_CSR_ADDR_WIDTH'('h301);
parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_MIE = SCR1_CSR_ADDR_WIDTH'('h304);
parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_MTVEC = SCR1_CSR_ADDR_WIDTH'('h305);
// Machine Trap Handling (read-write)
parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_MSCRATCH = SCR1_CSR_ADDR_WIDTH'('h340);
parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_MEPC = SCR1_CSR_ADDR_WIDTH'('h341);
parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_MCAUSE = SCR1_CSR_ADDR_WIDTH'('h342);
parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_MTVAL = SCR1_CSR_ADDR_WIDTH'('h343);
parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_MIP = SCR1_CSR_ADDR_WIDTH'('h344);
// Machine Counters/Timers (read-write)
`ifndef SCR1_CSR_REDUCED_CNT
parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_MCYCLE = SCR1_CSR_ADDR_WIDTH'('hB00);
parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_MINSTRET = SCR1_CSR_ADDR_WIDTH'('hB02);
parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_MCYCLEH = SCR1_CSR_ADDR_WIDTH'('hB80);
parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_MINSTRETH = SCR1_CSR_ADDR_WIDTH'('hB82);
`endif // SCR1_CSR_REDUCED_CNT
// Shadow Counters/Timers (read-only)
parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_TIME = SCR1_CSR_ADDR_WIDTH'('hC01);
`ifndef SCR1_CSR_REDUCED_CNT
parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_CYCLE = SCR1_CSR_ADDR_WIDTH'('hC00);
parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_INSTRET = SCR1_CSR_ADDR_WIDTH'('hC02);
parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_TIMEH = SCR1_CSR_ADDR_WIDTH'('hC81);
parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_CYCLEH = SCR1_CSR_ADDR_WIDTH'('hC80);
parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_INSTRETH = SCR1_CSR_ADDR_WIDTH'('hC82);
`endif // SCR1_CSR_REDUCED_CNT
`ifdef SCR1_DBG_EN
//parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_DBGC_SCRATCH = 'h7C8;
parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_HDU_MBASE = SCR1_CSR_ADDR_WIDTH'('h7B0);
parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_HDU_MSPAN = SCR1_CSR_ADDR_WIDTH'('h004); // must be power of 2
`endif // SCR1_DBG_EN
//-------------------------------------------------------------------------------
// CSR addresses (non-standard)
//-------------------------------------------------------------------------------
`ifdef SCR1_MCOUNTEN_EN
parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_MCOUNTEN = SCR1_CSR_ADDR_WIDTH'('h7E0);
`endif // SCR1_MCOUNTEN_EN
`ifdef SCR1_TDU_EN
parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_TDU_MBASE = SCR1_CSR_ADDR_WIDTH'('h7A0);
parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_TDU_MSPAN = SCR1_CSR_ADDR_WIDTH'('h008); // must be power of 2
`endif // SCR1_TDU_EN
`ifdef SCR1_IPIC_EN
parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_IPIC_BASE = SCR1_CSR_ADDR_WIDTH'('hBF0);
parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_IPIC_CISV = (SCR1_CSR_ADDR_IPIC_BASE + SCR1_IPIC_CISV );
parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_IPIC_CICSR = (SCR1_CSR_ADDR_IPIC_BASE + SCR1_IPIC_CICSR);
parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_IPIC_IPR = (SCR1_CSR_ADDR_IPIC_BASE + SCR1_IPIC_IPR );
parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_IPIC_ISVR = (SCR1_CSR_ADDR_IPIC_BASE + SCR1_IPIC_ISVR );
parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_IPIC_EOI = (SCR1_CSR_ADDR_IPIC_BASE + SCR1_IPIC_EOI );
parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_IPIC_SOI = (SCR1_CSR_ADDR_IPIC_BASE + SCR1_IPIC_SOI );
parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_IPIC_IDX = (SCR1_CSR_ADDR_IPIC_BASE + SCR1_IPIC_IDX );
parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_IPIC_ICSR = (SCR1_CSR_ADDR_IPIC_BASE + SCR1_IPIC_ICSR );
`endif // SCR1_IPIC_EN
//-------------------------------------------------------------------------------
// CSR definitions
//-------------------------------------------------------------------------------
// General
parameter bit [`SCR1_XLEN-1:0] SCR1_RST_VECTOR = SCR1_ARCH_RST_VECTOR;
// Reset values
parameter bit SCR1_CSR_MIE_MSIE_RST_VAL = 1'b0;
parameter bit SCR1_CSR_MIE_MTIE_RST_VAL = 1'b0;
parameter bit SCR1_CSR_MIE_MEIE_RST_VAL = 1'b0;
parameter bit SCR1_CSR_MIP_MSIP_RST_VAL = 1'b0;
parameter bit SCR1_CSR_MIP_MTIP_RST_VAL = 1'b0;
parameter bit SCR1_CSR_MIP_MEIP_RST_VAL = 1'b0;
parameter bit SCR1_CSR_MSTATUS_MIE_RST_VAL = 1'b0;
parameter bit SCR1_CSR_MSTATUS_MPIE_RST_VAL = 1'b1;
// MISA
`define SCR1_RVC_ENC `SCR1_XLEN'h0004
`define SCR1_RVE_ENC `SCR1_XLEN'h0010
`define SCR1_RVI_ENC `SCR1_XLEN'h0100
`define SCR1_RVM_ENC `SCR1_XLEN'h1000
parameter bit [1:0] SCR1_MISA_MXL_32 = 2'd1;
parameter bit [`SCR1_XLEN-1:0] SCR1_CSR_MISA = (SCR1_MISA_MXL_32 << (`SCR1_XLEN-2))
`ifndef SCR1_RVE_EXT
| `SCR1_RVI_ENC
`else // SCR1_RVE_EXT
| `SCR1_RVE_ENC
`endif // SCR1_RVE_EXT
`ifdef SCR1_RVC_EXT
| `SCR1_RVC_ENC
`endif // SCR1_RVC_EXT
`ifdef SCR1_RVM_EXT
| `SCR1_RVM_ENC
`endif // SCR1_RVM_EXT
;
// MVENDORID
parameter bit [`SCR1_XLEN-1:0] SCR1_CSR_MVENDORID = `SCR1_MVENDORID;
// MARCHID
parameter bit [`SCR1_XLEN-1:0] SCR1_CSR_MARCHID = `SCR1_XLEN'd8;
// MIMPID
parameter bit [`SCR1_XLEN-1:0] SCR1_CSR_MIMPID = `SCR1_MIMPID;
// MSTATUS
parameter bit [1:0] SCR1_CSR_MSTATUS_MPP = 2'b11;
parameter int unsigned SCR1_CSR_MSTATUS_MIE_OFFSET = 3;
parameter int unsigned SCR1_CSR_MSTATUS_MPIE_OFFSET = 7;
parameter int unsigned SCR1_CSR_MSTATUS_MPP_OFFSET = 11;
// MTVEC
// bits [5:0] are always zero
parameter bit [`SCR1_XLEN-1:SCR1_CSR_MTVEC_BASE_ZERO_BITS] SCR1_CSR_MTVEC_BASE_RST_VAL = SCR1_CSR_MTVEC_BASE_WR_RST_VAL;
parameter bit SCR1_CSR_MTVEC_MODE_DIRECT = 1'b0;
`ifdef SCR1_MTVEC_MODE_EN
parameter bit SCR1_CSR_MTVEC_MODE_VECTORED = 1'b1;
`endif // SCR1_MTVEC_MODE_EN
// MIE, MIP
parameter int unsigned SCR1_CSR_MIE_MSIE_OFFSET = 3;
parameter int unsigned SCR1_CSR_MIE_MTIE_OFFSET = 7;
parameter int unsigned SCR1_CSR_MIE_MEIE_OFFSET = 11;
`ifdef SCR1_MCOUNTEN_EN
// MCOUNTEN
parameter int unsigned SCR1_CSR_MCOUNTEN_CY_OFFSET = 0;
parameter int unsigned SCR1_CSR_MCOUNTEN_IR_OFFSET = 2;
`endif // SCR1_MCOUNTEN_EN
// MCAUSE
typedef logic [`SCR1_XLEN-2:0] type_scr1_csr_mcause_ec_v;
// MCYCLE, MINSTRET
`ifdef SCR1_CSR_REDUCED_CNT
parameter int unsigned SCR1_CSR_COUNTERS_WIDTH = 32;
`else // ~SCR1_CSR_REDUCED_CNT
parameter int unsigned SCR1_CSR_COUNTERS_WIDTH = 64;
`endif // ~SCR1_CSR_REDUCED_CNT
// HPM
parameter bit [6:0] SCR1_CSR_ADDR_HPMCOUNTER_MASK = 7'b1100000;
parameter bit [6:0] SCR1_CSR_ADDR_HPMCOUNTERH_MASK = 7'b1100100;
parameter bit [6:0] SCR1_CSR_ADDR_MHPMCOUNTER_MASK = 7'b1011000;
parameter bit [6:0] SCR1_CSR_ADDR_MHPMCOUNTERH_MASK = 7'b1011100;
parameter bit [6:0] SCR1_CSR_ADDR_MHPMEVENT_MASK = 7'b0011001;
//-------------------------------------------------------------------------------
// Types declaration
//-------------------------------------------------------------------------------
typedef enum logic {
SCR1_CSR_RESP_OK,
SCR1_CSR_RESP_ER
`ifdef SCR1_XPROP_EN
,
SCR1_CSR_RESP_ERROR = 'x
`endif // SCR1_XPROP_EN
} type_scr1_csr_resp_e;
`endif // SCR1_CSR_SVH

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/// Copyright by Syntacore LLC © 2016-2021. See LICENSE for details
/// @file <scr1_dm.svh>
/// @brief Debug Module header file
///
`ifndef SCR1_INCLUDE_DM_DEFS
`define SCR1_INCLUDE_DM_DEFS
`include "scr1_arch_description.svh"
`include "scr1_hdu.svh"
`include "scr1_csr.svh"
parameter SCR1_DBG_DMI_ADDR_WIDTH = 6'd7;
parameter SCR1_DBG_DMI_DATA_WIDTH = 6'd32;
parameter SCR1_DBG_DMI_OP_WIDTH = 2'd2;
parameter SCR1_DBG_DMI_CH_ID_WIDTH = 2'd2;
parameter SCR1_DBG_DMI_DR_DTMCS_WIDTH = 6'd32;
parameter SCR1_DBG_DMI_DR_DMI_ACCESS_WIDTH = SCR1_DBG_DMI_OP_WIDTH +
SCR1_DBG_DMI_DATA_WIDTH +
SCR1_DBG_DMI_ADDR_WIDTH;
// Debug Module addresses
parameter SCR1_DBG_DATA0 = 7'h4;
parameter SCR1_DBG_DATA1 = 7'h5;
parameter SCR1_DBG_DMCONTROL = 7'h10;
parameter SCR1_DBG_DMSTATUS = 7'h11;
parameter SCR1_DBG_HARTINFO = 7'h12;
parameter SCR1_DBG_ABSTRACTCS = 7'h16;
parameter SCR1_DBG_COMMAND = 7'h17;
parameter SCR1_DBG_ABSTRACTAUTO = 7'h18;
parameter SCR1_DBG_PROGBUF0 = 7'h20;
parameter SCR1_DBG_PROGBUF1 = 7'h21;
parameter SCR1_DBG_PROGBUF2 = 7'h22;
parameter SCR1_DBG_PROGBUF3 = 7'h23;
parameter SCR1_DBG_PROGBUF4 = 7'h24;
parameter SCR1_DBG_PROGBUF5 = 7'h25;
parameter SCR1_DBG_HALTSUM0 = 7'h40;
// DMCONTROL
parameter SCR1_DBG_DMCONTROL_HALTREQ = 5'd31;
parameter SCR1_DBG_DMCONTROL_RESUMEREQ = 5'd30;
parameter SCR1_DBG_DMCONTROL_HARTRESET = 5'd29;
parameter SCR1_DBG_DMCONTROL_ACKHAVERESET = 5'd28;
parameter SCR1_DBG_DMCONTROL_RESERVEDB = 5'd27;
parameter SCR1_DBG_DMCONTROL_HASEL = 5'd26;
parameter SCR1_DBG_DMCONTROL_HARTSELLO_HI = 5'd25;
parameter SCR1_DBG_DMCONTROL_HARTSELLO_LO = 5'd16;
parameter SCR1_DBG_DMCONTROL_HARTSELHI_HI = 5'd15;
parameter SCR1_DBG_DMCONTROL_HARTSELHI_LO = 5'd6;
parameter SCR1_DBG_DMCONTROL_RESERVEDA_HI = 5'd5;
parameter SCR1_DBG_DMCONTROL_RESERVEDA_LO = 5'd2;
parameter SCR1_DBG_DMCONTROL_NDMRESET = 5'd1;
parameter SCR1_DBG_DMCONTROL_DMACTIVE = 5'd0;
// DMSTATUS
parameter SCR1_DBG_DMSTATUS_RESERVEDC_HI = 5'd31;
parameter SCR1_DBG_DMSTATUS_RESERVEDC_LO = 5'd23;
parameter SCR1_DBG_DMSTATUS_IMPEBREAK = 5'd22;
parameter SCR1_DBG_DMSTATUS_RESERVEDB_HI = 5'd21;
parameter SCR1_DBG_DMSTATUS_RESERVEDB_LO = 5'd20;
parameter SCR1_DBG_DMSTATUS_ALLHAVERESET = 5'd19;
parameter SCR1_DBG_DMSTATUS_ANYHAVERESET = 5'd18;
parameter SCR1_DBG_DMSTATUS_ALLRESUMEACK = 5'd17;
parameter SCR1_DBG_DMSTATUS_ANYRESUMEACK = 5'd16;
parameter SCR1_DBG_DMSTATUS_ALLNONEXISTENT = 5'd15;
parameter SCR1_DBG_DMSTATUS_ANYNONEXISTENT = 5'd14;
parameter SCR1_DBG_DMSTATUS_ALLUNAVAIL = 5'd13;
parameter SCR1_DBG_DMSTATUS_ANYUNAVAIL = 5'd12;
parameter SCR1_DBG_DMSTATUS_ALLRUNNING = 5'd11;
parameter SCR1_DBG_DMSTATUS_ANYRUNNING = 5'd10;
parameter SCR1_DBG_DMSTATUS_ALLHALTED = 5'd9;
parameter SCR1_DBG_DMSTATUS_ANYHALTED = 5'd8;
parameter SCR1_DBG_DMSTATUS_AUTHENTICATED = 5'd7;
parameter SCR1_DBG_DMSTATUS_AUTHBUSY = 5'd6;
parameter SCR1_DBG_DMSTATUS_RESERVEDA = 5'd5;
parameter SCR1_DBG_DMSTATUS_DEVTREEVALID = 5'd4;
parameter SCR1_DBG_DMSTATUS_VERSION_HI = 5'd3;
parameter SCR1_DBG_DMSTATUS_VERSION_LO = 5'd0;
// COMMANDS
parameter SCR1_DBG_COMMAND_TYPE_HI = 5'd31;
parameter SCR1_DBG_COMMAND_TYPE_LO = 5'd24;
parameter SCR1_DBG_COMMAND_TYPE_WDTH = SCR1_DBG_COMMAND_TYPE_HI
- SCR1_DBG_COMMAND_TYPE_LO;
parameter SCR1_DBG_COMMAND_ACCESSREG_RESERVEDB = 5'd23;
parameter SCR1_DBG_COMMAND_ACCESSREG_SIZE_HI = 5'd22;
parameter SCR1_DBG_COMMAND_ACCESSREG_SIZE_LO = 5'd20;
parameter SCR1_DBG_COMMAND_ACCESSREG_SIZE_WDTH = SCR1_DBG_COMMAND_ACCESSREG_SIZE_HI
- SCR1_DBG_COMMAND_ACCESSREG_SIZE_LO;
parameter SCR1_DBG_COMMAND_ACCESSREG_RESERVEDA = 5'd19;
parameter SCR1_DBG_COMMAND_ACCESSREG_POSTEXEC = 5'd18;
parameter SCR1_DBG_COMMAND_ACCESSREG_TRANSFER = 5'd17;
parameter SCR1_DBG_COMMAND_ACCESSREG_WRITE = 5'd16;
parameter SCR1_DBG_COMMAND_ACCESSREG_REGNO_HI = 5'd15;
parameter SCR1_DBG_COMMAND_ACCESSREG_REGNO_LO = 5'd0;
parameter SCR1_DBG_COMMAND_ACCESSMEM_AAMVIRTUAL = 5'd23;
parameter SCR1_DBG_COMMAND_ACCESSMEM_AAMSIZE_HI = 5'd22;
parameter SCR1_DBG_COMMAND_ACCESSMEM_AAMSIZE_LO = 5'd20;
parameter SCR1_DBG_COMMAND_ACCESSMEM_AAMPOSTINC = 5'd19;
parameter SCR1_DBG_COMMAND_ACCESSMEM_RESERVEDB_HI = 5'd18;
parameter SCR1_DBG_COMMAND_ACCESSMEM_RESERVEDB_LO = 5'd17;
parameter SCR1_DBG_COMMAND_ACCESSMEM_WRITE = 5'd16;
parameter SCR1_DBG_COMMAND_ACCESSMEM_RESERVEDA_HI = 5'd13;
parameter SCR1_DBG_COMMAND_ACCESSMEM_RESERVEDA_LO = 5'd0;
// ABSTRACTCS
parameter SCR1_DBG_ABSTRACTCS_RESERVEDD_HI = 5'd31;
parameter SCR1_DBG_ABSTRACTCS_RESERVEDD_LO = 5'd29;
parameter SCR1_DBG_ABSTRACTCS_PROGBUFSIZE_HI = 5'd28;
parameter SCR1_DBG_ABSTRACTCS_PROGBUFSIZE_LO = 5'd24;
parameter SCR1_DBG_ABSTRACTCS_RESERVEDC_HI = 5'd23;
parameter SCR1_DBG_ABSTRACTCS_RESERVEDC_LO = 5'd13;
parameter SCR1_DBG_ABSTRACTCS_BUSY = 5'd12;
parameter SCR1_DBG_ABSTRACTCS_RESERVEDB = 5'd11;
parameter SCR1_DBG_ABSTRACTCS_CMDERR_HI = 5'd10;
parameter SCR1_DBG_ABSTRACTCS_CMDERR_LO = 5'd8;
parameter SCR1_DBG_ABSTRACTCS_CMDERR_WDTH = SCR1_DBG_ABSTRACTCS_CMDERR_HI
- SCR1_DBG_ABSTRACTCS_CMDERR_LO;
parameter SCR1_DBG_ABSTRACTCS_RESERVEDA_HI = 5'd7;
parameter SCR1_DBG_ABSTRACTCS_RESERVEDA_LO = 5'd4;
parameter SCR1_DBG_ABSTRACTCS_DATACOUNT_HI = 5'd3;
parameter SCR1_DBG_ABSTRACTCS_DATACOUNT_LO = 5'd0;
// HARTINFO
parameter SCR1_DBG_HARTINFO_RESERVEDB_HI = 5'd31;
parameter SCR1_DBG_HARTINFO_RESERVEDB_LO = 5'd24;
parameter SCR1_DBG_HARTINFO_NSCRATCH_HI = 5'd23;
parameter SCR1_DBG_HARTINFO_NSCRATCH_LO = 5'd20;
parameter SCR1_DBG_HARTINFO_RESERVEDA_HI = 5'd19;
parameter SCR1_DBG_HARTINFO_RESERVEDA_LO = 5'd17;
parameter SCR1_DBG_HARTINFO_DATAACCESS = 5'd16;
parameter SCR1_DBG_HARTINFO_DATASIZE_HI = 5'd15;
parameter SCR1_DBG_HARTINFO_DATASIZE_LO = 5'd12;
parameter SCR1_DBG_HARTINFO_DATAADDR_HI = 5'd11;
parameter SCR1_DBG_HARTINFO_DATAADDR_LO = 5'd0;
`endif // SCR1_INCLUDE_DM_DEFS

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/// Copyright by Syntacore LLC © 2016-2021. See LICENSE for details
/// @file <scr1_pipe_hdu.svh>
/// @brief HART Debug Unit definitions file
///
`ifdef SCR1_DBG_EN
`ifndef SCR1_INCLUDE_HDU_DEFS
`define SCR1_INCLUDE_HDU_DEFS
`include "scr1_arch_description.svh"
`include "scr1_csr.svh"
`ifdef SCR1_MMU_EN
`define SCR1_HDU_FEATURE_MPRVEN
`endif // SCR1_MMU_EN
//==============================================================================
// Parameters
//==============================================================================
//localparam int unsigned SCR1_HDU_DEBUGCSR_BASE_ADDR = 12'h7B0;
localparam int unsigned SCR1_HDU_DEBUGCSR_ADDR_SPAN = SCR1_CSR_ADDR_HDU_MSPAN;
localparam int unsigned SCR1_HDU_DEBUGCSR_ADDR_WIDTH = $clog2(SCR1_HDU_DEBUGCSR_ADDR_SPAN);
localparam bit [3:0] SCR1_HDU_DEBUGCSR_DCSR_XDEBUGVER = 4'h4;
localparam int unsigned SCR1_HDU_PBUF_ADDR_SPAN = 8;
localparam int unsigned SCR1_HDU_PBUF_ADDR_WIDTH = $clog2(SCR1_HDU_PBUF_ADDR_SPAN);
localparam int unsigned SCR1_HDU_DATA_REG_WIDTH = 32;
localparam int unsigned SCR1_HDU_CORE_INSTR_WIDTH = 32;
//==============================================================================
// Types
//==============================================================================
// HART Debug States:
typedef enum logic [1:0] {
SCR1_HDU_DBGSTATE_RESET = 2'b00,
SCR1_HDU_DBGSTATE_RUN = 2'b01,
SCR1_HDU_DBGSTATE_DHALTED = 2'b10,
SCR1_HDU_DBGSTATE_DRUN = 2'b11
`ifdef SCR1_XPROP_EN
,
SCR1_HDU_DBGSTATE_XXX = 'X
`endif // SCR1_XPROP_EN
} type_scr1_hdu_dbgstates_e;
typedef enum logic [1:0] {
SCR1_HDU_PBUFSTATE_IDLE = 2'b00,
SCR1_HDU_PBUFSTATE_FETCH = 2'b01,
SCR1_HDU_PBUFSTATE_EXCINJECT = 2'b10,
SCR1_HDU_PBUFSTATE_WAIT4END = 2'b11
`ifdef SCR1_XPROP_EN
,
SCR1_HDU_PBUFSTATE_XXX = 'X
`endif // SCR1_XPROP_EN
} type_scr1_hdu_pbufstates_e;
typedef enum logic {
SCR1_HDU_HARTCMD_RESUME = 1'b0,
SCR1_HDU_HARTCMD_HALT = 1'b1
`ifdef SCR1_XPROP_EN
,
SCR1_HDU_HARTCMD_XXX = 1'bX
`endif // SCR1_XPROP_EN
} type_scr1_hdu_hart_command_e;
typedef enum logic {
SCR1_HDU_FETCH_SRC_NORMAL = 1'b0,
SCR1_HDU_FETCH_SRC_PBUF = 1'b1
`ifdef SCR1_XPROP_EN
,
SCR1_HDU_FETCH_SRC_XXX = 1'bX
`endif // SCR1_XPROP_EN
} type_scr1_hdu_fetch_src_e;
typedef struct packed {
//logic reset_n;
logic except;
logic ebreak;
type_scr1_hdu_dbgstates_e dbg_state;
} type_scr1_hdu_hartstatus_s;
// Debug Mode Redirection control:
typedef struct packed {
logic sstep; // Single Step
logic ebreak; // Redirection after EBREAK execution
} type_scr1_hdu_redirect_s;
typedef struct packed {
logic irq_dsbl;
type_scr1_hdu_fetch_src_e fetch_src;
logic pc_advmt_dsbl;
logic hwbrkpt_dsbl;
type_scr1_hdu_redirect_s redirect;
} type_scr1_hdu_runctrl_s;
// HART Halt Status:
typedef enum logic [2:0] {
SCR1_HDU_HALTCAUSE_NONE = 3'b000,
SCR1_HDU_HALTCAUSE_EBREAK = 3'b001,
SCR1_HDU_HALTCAUSE_TMREQ = 3'b010,
SCR1_HDU_HALTCAUSE_DMREQ = 3'b011,
SCR1_HDU_HALTCAUSE_SSTEP = 3'b100,
SCR1_HDU_HALTCAUSE_RSTEXIT = 3'b101
`ifdef SCR1_XPROP_EN
,
SCR1_HDU_HALTCAUSE_XXX = 'X
`endif // SCR1_XPROP_EN
} type_scr1_hdu_haltcause_e;
typedef struct packed {
logic except;
type_scr1_hdu_haltcause_e cause;
} type_scr1_hdu_haltstatus_s;
// Debug CSR map
localparam SCR1_HDU_DBGCSR_OFFS_DCSR = SCR1_HDU_DEBUGCSR_ADDR_WIDTH'( 'd0 );
localparam SCR1_HDU_DBGCSR_OFFS_DPC = SCR1_HDU_DEBUGCSR_ADDR_WIDTH'( 'd1 );
localparam SCR1_HDU_DBGCSR_OFFS_DSCRATCH0 = SCR1_HDU_DEBUGCSR_ADDR_WIDTH'( 'd2 );
localparam SCR1_HDU_DBGCSR_OFFS_DSCRATCH1 = SCR1_HDU_DEBUGCSR_ADDR_WIDTH'( 'd3 );
localparam bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_HDU_DBGCSR_ADDR_DCSR = SCR1_CSR_ADDR_HDU_MBASE + SCR1_HDU_DBGCSR_OFFS_DCSR;
localparam bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_HDU_DBGCSR_ADDR_DPC = SCR1_CSR_ADDR_HDU_MBASE + SCR1_HDU_DBGCSR_OFFS_DPC;
localparam bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_HDU_DBGCSR_ADDR_DSCRATCH0 = SCR1_CSR_ADDR_HDU_MBASE + SCR1_HDU_DBGCSR_OFFS_DSCRATCH0;
localparam bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_HDU_DBGCSR_ADDR_DSCRATCH1 = SCR1_CSR_ADDR_HDU_MBASE + SCR1_HDU_DBGCSR_OFFS_DSCRATCH1;
// Debug CSRs :: DCSR
typedef enum int {
SCR1_HDU_DCSR_PRV_BIT_R = 0,
SCR1_HDU_DCSR_PRV_BIT_L = 1,
SCR1_HDU_DCSR_STEP_BIT = 2,
SCR1_HDU_DCSR_RSRV0_BIT_R = 3,
SCR1_HDU_DCSR_RSRV0_BIT_L = 5,
SCR1_HDU_DCSR_CAUSE_BIT_R = 6,
SCR1_HDU_DCSR_CAUSE_BIT_L = 8,
SCR1_HDU_DCSR_RSRV1_BIT_R = 9,
SCR1_HDU_DCSR_RSRV1_BIT_L = 10,
SCR1_HDU_DCSR_STEPIE_BIT = 11,
SCR1_HDU_DCSR_RSRV2_BIT_R = 12,
SCR1_HDU_DCSR_RSRV2_BIT_L = 14,
SCR1_HDU_DCSR_EBREAKM_BIT = 15,
SCR1_HDU_DCSR_RSRV3_BIT_R = 16,
SCR1_HDU_DCSR_RSRV3_BIT_L = 27,
SCR1_HDU_DCSR_XDEBUGVER_BIT_R = 28,
SCR1_HDU_DCSR_XDEBUGVER_BIT_L = 31
} type_scr1_hdu_dcsr_bits_e;
//localparam int unsigned SCR1_HDU_DEBUGCSR_DCSR_PRV_WIDTH = SCR1_HDU_DCSR_PRV_BIT_L-SCR1_HDU_DCSR_PRV_BIT_R+1;
typedef struct packed {
logic [SCR1_HDU_DCSR_XDEBUGVER_BIT_L-SCR1_HDU_DCSR_XDEBUGVER_BIT_R:0] xdebugver;
logic [SCR1_HDU_DCSR_RSRV3_BIT_L-SCR1_HDU_DCSR_RSRV3_BIT_R:0] rsrv3;
logic ebreakm;
logic [SCR1_HDU_DCSR_RSRV2_BIT_L-SCR1_HDU_DCSR_RSRV2_BIT_R:0] rsrv2;
logic stepie;
logic [SCR1_HDU_DCSR_RSRV1_BIT_L-SCR1_HDU_DCSR_RSRV1_BIT_R:0] rsrv1;
logic [SCR1_HDU_DCSR_CAUSE_BIT_L-SCR1_HDU_DCSR_CAUSE_BIT_R:0] cause;
logic [SCR1_HDU_DCSR_RSRV0_BIT_L-SCR1_HDU_DCSR_RSRV0_BIT_R:0] rsrv0;
logic step;
logic [SCR1_HDU_DCSR_PRV_BIT_L-SCR1_HDU_DCSR_PRV_BIT_R:0] prv;
} type_scr1_hdu_dcsr_s;
`endif // SCR1_INCLUDE_HDU_DEFS
`endif // SCR1_DBG_EN

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/// Copyright by Syntacore LLC © 2016-2021. See LICENSE for details
/// @file <scr1_ipic.svh>
/// @brief IPIC header file
///
`ifndef SCR1_IPIC_SVH
`define SCR1_IPIC_SVH
`include "scr1_arch_description.svh"
`ifdef SCR1_IPIC_EN
//-------------------------------------------------------------------------------
// Parameters declaration
//-------------------------------------------------------------------------------
parameter SCR1_IRQ_VECT_NUM = 16; // must be power of 2 in the current implementation
parameter SCR1_IRQ_VECT_WIDTH = $clog2(SCR1_IRQ_VECT_NUM+1);
parameter SCR1_IRQ_LINES_NUM = SCR1_IRQ_VECT_NUM;
parameter SCR1_IRQ_LINES_WIDTH = $clog2(SCR1_IRQ_LINES_NUM);
parameter logic [SCR1_IRQ_VECT_WIDTH-1:0] SCR1_IRQ_VOID_VECT_NUM = SCR1_IRQ_VECT_WIDTH'(SCR1_IRQ_VECT_NUM);
parameter SCR1_IRQ_IDX_WIDTH = $clog2(SCR1_IRQ_VECT_NUM);
// Address decoding parameters
parameter logic [2:0] SCR1_IPIC_CISV = 3'h0; // RO
parameter logic [2:0] SCR1_IPIC_CICSR = 3'h1; // {IP, IE}
parameter logic [2:0] SCR1_IPIC_IPR = 3'h2; // RW1C
parameter logic [2:0] SCR1_IPIC_ISVR = 3'h3; // RO
parameter logic [2:0] SCR1_IPIC_EOI = 3'h4; // RZW
parameter logic [2:0] SCR1_IPIC_SOI = 3'h5; // RZW
parameter logic [2:0] SCR1_IPIC_IDX = 3'h6; // RW
parameter logic [2:0] SCR1_IPIC_ICSR = 3'h7; // RW
parameter SCR1_IPIC_ICSR_IP = 0;
parameter SCR1_IPIC_ICSR_IE = 1;
parameter SCR1_IPIC_ICSR_IM = 2;
parameter SCR1_IPIC_ICSR_INV = 3;
parameter SCR1_IPIC_ICSR_IS = 4;
parameter SCR1_IPIC_ICSR_PRV_LSB = 8;
parameter SCR1_IPIC_ICSR_PRV_MSB = 9;
parameter SCR1_IPIC_ICSR_LN_LSB = 12;
parameter SCR1_IPIC_ICSR_LN_MSB = SCR1_IPIC_ICSR_LN_LSB
+ SCR1_IRQ_LINES_WIDTH;
parameter logic [1:0] SCR1_IPIC_PRV_M = 2'b11;
//-------------------------------------------------------------------------------
// Types declaration
//-------------------------------------------------------------------------------
typedef enum logic {
SCR1_CSR2IPIC_RD,
SCR1_CSR2IPIC_WR
`ifdef SCR1_XPROP_EN
,
SCR1_CSR2IPIC_ERROR = 'x
`endif // SCR1_XPROP_EN
} type_scr1_csr2ipic_wr_e;
`endif // SCR1_IPIC_EN
`endif // SCR1_IPIC_SVH

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/// Copyright by Syntacore LLC © 2016-2021. See LICENSE for details
/// @file <scr1_memif.svh>
/// @brief Memory interface definitions file
///
`ifndef SCR1_MEMIF_SVH
`define SCR1_MEMIF_SVH
`include "scr1_arch_description.svh"
//-------------------------------------------------------------------------------
// Memory command enum
//-------------------------------------------------------------------------------
typedef enum logic {
SCR1_MEM_CMD_RD = 1'b0,
SCR1_MEM_CMD_WR = 1'b1
`ifdef SCR1_XPROP_EN
,
SCR1_MEM_CMD_ERROR = 'x
`endif // SCR1_XPROP_EN
} type_scr1_mem_cmd_e;
//-------------------------------------------------------------------------------
// Memory data width enum
//-------------------------------------------------------------------------------
typedef enum logic[1:0] {
SCR1_MEM_WIDTH_BYTE = 2'b00,
SCR1_MEM_WIDTH_HWORD = 2'b01,
SCR1_MEM_WIDTH_WORD = 2'b10
`ifdef SCR1_XPROP_EN
,
SCR1_MEM_WIDTH_ERROR = 'x
`endif // SCR1_XPROP_EN
} type_scr1_mem_width_e;
//-------------------------------------------------------------------------------
// Memory response enum
//-------------------------------------------------------------------------------
typedef enum logic[1:0] {
SCR1_MEM_RESP_NOTRDY = 2'b00,
SCR1_MEM_RESP_RDY_OK = 2'b01,
SCR1_MEM_RESP_RDY_ER = 2'b10
`ifdef SCR1_XPROP_EN
,
SCR1_MEM_RESP_ERROR = 'x
`endif // SCR1_XPROP_EN
} type_scr1_mem_resp_e;
`endif // SCR1_MEMIF_SVH

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/// Copyright by Syntacore LLC © 2016-2021. See LICENSE for details
/// @file <scr1_riscv_isa_decoding.svh>
/// @brief RISC-V ISA definitions file
///
`ifndef SCR1_RISCV_ISA_DECODING_SVH
`define SCR1_RISCV_ISA_DECODING_SVH
`include "scr1_arch_description.svh"
`include "scr1_arch_types.svh"
//-------------------------------------------------------------------------------
// Instruction types
//-------------------------------------------------------------------------------
typedef enum logic [1:0] {
SCR1_INSTR_RVC0 = 2'b00,
SCR1_INSTR_RVC1 = 2'b01,
SCR1_INSTR_RVC2 = 2'b10,
SCR1_INSTR_RVI = 2'b11
} type_scr1_instr_type_e;
//-------------------------------------------------------------------------------
// RV32I opcodes (bits 6:2)
//-------------------------------------------------------------------------------
typedef enum logic [6:2] {
SCR1_OPCODE_LOAD = 5'b00000,
SCR1_OPCODE_MISC_MEM = 5'b00011,
SCR1_OPCODE_OP_IMM = 5'b00100,
SCR1_OPCODE_AUIPC = 5'b00101,
SCR1_OPCODE_STORE = 5'b01000,
SCR1_OPCODE_OP = 5'b01100,
SCR1_OPCODE_LUI = 5'b01101,
SCR1_OPCODE_BRANCH = 5'b11000,
SCR1_OPCODE_JALR = 5'b11001,
SCR1_OPCODE_JAL = 5'b11011,
SCR1_OPCODE_SYSTEM = 5'b11100
} type_scr1_rvi_opcode_e;
//-------------------------------------------------------------------------------
// IALU main operands
//-------------------------------------------------------------------------------
localparam SCR1_IALU_OP_ALL_NUM_E = 2;
localparam SCR1_IALU_OP_WIDTH_E = $clog2(SCR1_IALU_OP_ALL_NUM_E);
typedef enum logic [SCR1_IALU_OP_WIDTH_E-1:0] {
SCR1_IALU_OP_REG_IMM, // op1 = rs1; op2 = imm
SCR1_IALU_OP_REG_REG // op1 = rs1; op2 = rs2
} type_scr1_ialu_op_sel_e;
//-------------------------------------------------------------------------------
// IALU main commands
//-------------------------------------------------------------------------------
`ifdef SCR1_RVM_EXT
localparam SCR1_IALU_CMD_ALL_NUM_E = 23;
`else // ~SCR1_RVM_EXT
localparam SCR1_IALU_CMD_ALL_NUM_E = 15;
`endif // ~SCR1_RVM_EXT
localparam SCR1_IALU_CMD_WIDTH_E = $clog2(SCR1_IALU_CMD_ALL_NUM_E);
typedef enum logic [SCR1_IALU_CMD_WIDTH_E-1:0] {
SCR1_IALU_CMD_NONE = '0, // IALU disable
SCR1_IALU_CMD_AND, // op1 & op2
SCR1_IALU_CMD_OR, // op1 | op2
SCR1_IALU_CMD_XOR, // op1 ^ op2
SCR1_IALU_CMD_ADD, // op1 + op2
SCR1_IALU_CMD_SUB, // op1 - op2
SCR1_IALU_CMD_SUB_LT, // op1 < op2
SCR1_IALU_CMD_SUB_LTU, // op1 u< op2
SCR1_IALU_CMD_SUB_EQ, // op1 = op2
SCR1_IALU_CMD_SUB_NE, // op1 != op2
SCR1_IALU_CMD_SUB_GE, // op1 >= op2
SCR1_IALU_CMD_SUB_GEU, // op1 u>= op2
SCR1_IALU_CMD_SLL, // op1 << op2
SCR1_IALU_CMD_SRL, // op1 >> op2
SCR1_IALU_CMD_SRA // op1 >>> op2
`ifdef SCR1_RVM_EXT
,
SCR1_IALU_CMD_MUL, // low(unsig(op1) * unsig(op2))
SCR1_IALU_CMD_MULHU, // high(unsig(op1) * unsig(op2))
SCR1_IALU_CMD_MULHSU, // high(op1 * unsig(op2))
SCR1_IALU_CMD_MULH, // high(op1 * op2)
SCR1_IALU_CMD_DIV, // op1 / op2
SCR1_IALU_CMD_DIVU, // op1 u/ op2
SCR1_IALU_CMD_REM, // op1 % op2
SCR1_IALU_CMD_REMU // op1 u% op2
`endif // SCR1_RVM_EXT
} type_scr1_ialu_cmd_sel_e;
//-------------------------------------------------------------------------------
// IALU SUM2 operands (result is JUMP/BRANCH target, LOAD/STORE address)
//-------------------------------------------------------------------------------
localparam SCR1_SUM2_OP_ALL_NUM_E = 2;
localparam SCR1_SUM2_OP_WIDTH_E = $clog2(SCR1_SUM2_OP_ALL_NUM_E);
typedef enum logic [SCR1_SUM2_OP_WIDTH_E-1:0] {
SCR1_SUM2_OP_PC_IMM, // op1 = curr_pc; op2 = imm (AUIPC, target new_pc for JAL and branches)
SCR1_SUM2_OP_REG_IMM // op1 = rs1; op2 = imm (target new_pc for JALR, LOAD/STORE address)
`ifdef SCR1_XPROP_EN
,
SCR1_SUM2_OP_ERROR = 'x
`endif // SCR1_XPROP_EN
} type_scr1_ialu_sum2_op_sel_e;
//-------------------------------------------------------------------------------
// LSU commands
//-------------------------------------------------------------------------------
localparam SCR1_LSU_CMD_ALL_NUM_E = 9;
localparam SCR1_LSU_CMD_WIDTH_E = $clog2(SCR1_LSU_CMD_ALL_NUM_E);
typedef enum logic [SCR1_LSU_CMD_WIDTH_E-1:0] {
SCR1_LSU_CMD_NONE = '0,
SCR1_LSU_CMD_LB,
SCR1_LSU_CMD_LH,
SCR1_LSU_CMD_LW,
SCR1_LSU_CMD_LBU,
SCR1_LSU_CMD_LHU,
SCR1_LSU_CMD_SB,
SCR1_LSU_CMD_SH,
SCR1_LSU_CMD_SW
} type_scr1_lsu_cmd_sel_e;
//-------------------------------------------------------------------------------
// CSR operands
//-------------------------------------------------------------------------------
localparam SCR1_CSR_OP_ALL_NUM_E = 2;
localparam SCR1_CSR_OP_WIDTH_E = $clog2(SCR1_CSR_OP_ALL_NUM_E);
typedef enum logic [SCR1_CSR_OP_WIDTH_E-1:0] {
SCR1_CSR_OP_IMM,
SCR1_CSR_OP_REG
} type_scr1_csr_op_sel_e;
//-------------------------------------------------------------------------------
// CSR commands
//-------------------------------------------------------------------------------
localparam SCR1_CSR_CMD_ALL_NUM_E = 4;
localparam SCR1_CSR_CMD_WIDTH_E = $clog2(SCR1_CSR_CMD_ALL_NUM_E);
typedef enum logic [SCR1_CSR_CMD_WIDTH_E-1:0] {
SCR1_CSR_CMD_NONE = '0,
SCR1_CSR_CMD_WRITE,
SCR1_CSR_CMD_SET,
SCR1_CSR_CMD_CLEAR
} type_scr1_csr_cmd_sel_e;
//-------------------------------------------------------------------------------
// MPRF rd writeback source
//-------------------------------------------------------------------------------
localparam SCR1_RD_WB_ALL_NUM_E = 7;
localparam SCR1_RD_WB_WIDTH_E = $clog2(SCR1_RD_WB_ALL_NUM_E);
typedef enum logic [SCR1_RD_WB_WIDTH_E-1:0] {
SCR1_RD_WB_NONE = '0,
SCR1_RD_WB_IALU, // IALU main result
SCR1_RD_WB_SUM2, // IALU SUM2 result (AUIPC)
SCR1_RD_WB_IMM, // LUI
SCR1_RD_WB_INC_PC, // JAL(R)
SCR1_RD_WB_LSU, // Load from DMEM
SCR1_RD_WB_CSR // Read CSR
} type_scr1_rd_wb_sel_e;
//-------------------------------------------------------------------------------
// IDU to EXU full command structure
//-------------------------------------------------------------------------------
localparam SCR1_GPR_FIELD_WIDTH = 5;
typedef struct packed {
logic instr_rvc; // used with a different meaning for IFU access fault exception
type_scr1_ialu_op_sel_e ialu_op;
type_scr1_ialu_cmd_sel_e ialu_cmd;
type_scr1_ialu_sum2_op_sel_e sum2_op;
type_scr1_lsu_cmd_sel_e lsu_cmd;
type_scr1_csr_op_sel_e csr_op;
type_scr1_csr_cmd_sel_e csr_cmd;
type_scr1_rd_wb_sel_e rd_wb_sel;
logic jump_req;
logic branch_req;
logic mret_req;
logic fencei_req;
logic wfi_req;
logic [SCR1_GPR_FIELD_WIDTH-1:0] rs1_addr; // also used as zimm for CSRRxI instructions
logic [SCR1_GPR_FIELD_WIDTH-1:0] rs2_addr;
logic [SCR1_GPR_FIELD_WIDTH-1:0] rd_addr;
logic [`SCR1_XLEN-1:0] imm; // used as {funct3, CSR address} for CSR instructions
// used as instruction field for illegal instruction exception
logic exc_req;
type_scr1_exc_code_e exc_code;
} type_scr1_exu_cmd_s;
`endif // SCR1_RISCV_ISA_DECODING_SVH

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/// Copyright by Syntacore LLC © 2016-2021. See LICENSE for details
/// @file <scr1_scu.svh>
/// @brief SCU header file
///
`ifndef SCR1_INCLUDE_SCU_DEFS
`define SCR1_INCLUDE_SCU_DEFS
//`include "scr1_arch_description.svh"
`ifdef SCR1_DBG_EN
//==============================================================================
// Parameters
//==============================================================================
localparam int unsigned SCR1_SCU_DR_SYSCTRL_OP_WIDTH = 2;
localparam int unsigned SCR1_SCU_DR_SYSCTRL_ADDR_WIDTH = 2;
localparam int unsigned SCR1_SCU_DR_SYSCTRL_DATA_WIDTH = 4;
//==============================================================================
// Types
//==============================================================================
typedef enum logic [SCR1_SCU_DR_SYSCTRL_OP_WIDTH-1:0] {
SCR1_SCU_SYSCTRL_OP_WRITE = 2'h0,
SCR1_SCU_SYSCTRL_OP_READ = 2'h1,
SCR1_SCU_SYSCTRL_OP_SETBITS = 2'h2,
SCR1_SCU_SYSCTRL_OP_CLRBITS = 2'h3
`ifdef SCR1_XPROP_EN
,
SCR1_SCU_SYSCTRL_OP_XXX = 'X
`endif // SCR1_XPROP_EN
} type_scr1_scu_sysctrl_op_e;
typedef enum logic [SCR1_SCU_DR_SYSCTRL_ADDR_WIDTH-1:0] {
SCR1_SCU_SYSCTRL_ADDR_CONTROL = 2'h0,
SCR1_SCU_SYSCTRL_ADDR_MODE = 2'h1,
SCR1_SCU_SYSCTRL_ADDR_STATUS = 2'h2,
SCR1_SCU_SYSCTRL_ADDR_STICKY = 2'h3
`ifdef SCR1_XPROP_EN
,
SCR1_SCU_SYSCTRL_ADDR_XXX = 'X
`endif // SCR1_XPROP_EN
} type_scr1_scu_sysctrl_addr_e;
typedef struct packed {
logic [SCR1_SCU_DR_SYSCTRL_DATA_WIDTH-1:0] data;
logic [SCR1_SCU_DR_SYSCTRL_ADDR_WIDTH-1:0] addr;
logic [SCR1_SCU_DR_SYSCTRL_OP_WIDTH-1:0] op;
} type_scr1_scu_sysctrl_dr_s;
typedef enum int unsigned {
SCR1_SCU_DR_SYSCTRL_OP_BIT_R = 'h0,
SCR1_SCU_DR_SYSCTRL_OP_BIT_L = SCR1_SCU_DR_SYSCTRL_OP_WIDTH-1,
SCR1_SCU_DR_SYSCTRL_ADDR_BIT_R = SCR1_SCU_DR_SYSCTRL_OP_WIDTH,
SCR1_SCU_DR_SYSCTRL_ADDR_BIT_L = SCR1_SCU_DR_SYSCTRL_OP_WIDTH +
SCR1_SCU_DR_SYSCTRL_ADDR_WIDTH - 1,
SCR1_SCU_DR_SYSCTRL_DATA_BIT_R = SCR1_SCU_DR_SYSCTRL_OP_WIDTH +
SCR1_SCU_DR_SYSCTRL_ADDR_WIDTH,
SCR1_SCU_DR_SYSCTRL_DATA_BIT_L = SCR1_SCU_DR_SYSCTRL_OP_WIDTH +
SCR1_SCU_DR_SYSCTRL_ADDR_WIDTH +
SCR1_SCU_DR_SYSCTRL_DATA_WIDTH - 1
} type_scr1_scu_sysctrl_dr_bits_e;
typedef struct packed {
logic [1:0] rsrv;
logic core_reset;
logic sys_reset;
} type_scr1_scu_sysctrl_control_reg_s;
typedef struct packed {
logic [1:0] rsrv;
logic hdu_rst_bhv;
logic dm_rst_bhv;
} type_scr1_scu_sysctrl_mode_reg_s;
typedef struct packed {
logic hdu_reset;
logic dm_reset;
logic core_reset;
logic sys_reset;
} type_scr1_scu_sysctrl_status_reg_s;
`endif // SCR1_DBG_EN
`endif // SCR1_INCLUDE_SCU_DEFS

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/// Copyright by Syntacore LLC © 2016-2021. See LICENSE for details
/// @file <scr1_search_ms1.svh>
/// @brief Most significant one search function
///
`ifndef SCR1_SEARCH_MS1_SVH
`define SCR1_SEARCH_MS1_SVH
//-------------------------------------------------------------------------------
// Local types declaration
//-------------------------------------------------------------------------------
typedef struct {
logic vd;
logic idx;
} type_scr1_search_one_2_s;
typedef struct {
logic vd;
logic [4:0] idx;
} type_scr1_search_one_32_s;
//-------------------------------------------------------------------------------
// Leading Zeros Count Function
//-------------------------------------------------------------------------------
function automatic type_scr1_search_one_2_s scr1_lead_zeros_cnt_2(
input logic [1:0] din
);
type_scr1_search_one_2_s tmp;
begin
tmp.vd = |din;
tmp.idx = ~din[1];
return tmp;
end
endfunction : scr1_lead_zeros_cnt_2
function automatic logic [4:0] scr1_lead_zeros_cnt_32(
input logic [31:0] din
);
begin
logic [15:0] stage1_vd;
logic [7:0] stage2_vd;
logic [3:0] stage3_vd;
logic [1:0] stage4_vd;
logic stage1_idx [15:0];
logic [1:0] stage2_idx [7:0];
logic [2:0] stage3_idx [3:0];
logic [3:0] stage4_idx [1:0];
type_scr1_search_one_32_s tmp;
logic [4:0] res;
// Stage 1
for (int unsigned i=0; i<16; ++i) begin
type_scr1_search_one_2_s tmp;
tmp = scr1_lead_zeros_cnt_2(din[(i+1)*2-1-:2]);
stage1_vd[i] = tmp.vd;
stage1_idx[i] = tmp.idx;
end
// Stage 2
for (int unsigned i=0; i<8; ++i) begin
type_scr1_search_one_2_s tmp;
tmp = scr1_lead_zeros_cnt_2(stage1_vd[(i+1)*2-1-:2]);
stage2_vd[i] = tmp.vd;
stage2_idx[i] = (tmp.idx) ? {tmp.idx, stage1_idx[2*i]} : {tmp.idx, stage1_idx[2*i+1]};
end
// Stage 3
for (int unsigned i=0; i<4; ++i) begin
type_scr1_search_one_2_s tmp;
tmp = scr1_lead_zeros_cnt_2(stage2_vd[(i+1)*2-1-:2]);
stage3_vd[i] = tmp.vd;
stage3_idx[i] = (tmp.idx) ? {tmp.idx, stage2_idx[2*i]} : {tmp.idx, stage2_idx[2*i+1]};
end
// Stage 4
for (int unsigned i=0; i<2; ++i) begin
type_scr1_search_one_2_s tmp;
tmp = scr1_lead_zeros_cnt_2(stage3_vd[(i+1)*2-1-:2]);
stage4_vd[i] = tmp.vd;
stage4_idx[i] = (tmp.idx) ? {tmp.idx, stage3_idx[2*i]} : {tmp.idx, stage3_idx[2*i+1]};
end
// Stage 5
tmp.vd = |stage4_vd;
tmp.idx = (stage4_vd[1]) ? {1'b0, stage4_idx[1]} : {1'b1, stage4_idx[0]};
res = tmp.idx;
return res;
end
endfunction : scr1_lead_zeros_cnt_32
`endif // SCR1_SEARCH_MS1_SVH

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/// Copyright by Syntacore LLC © 2016-2021. See LICENSE for details
/// @file <scr1_tapc.svh>
/// @brief TAPC header file
///
`ifndef SCR1_INCLUDE_TAPC_DEFS
`define SCR1_INCLUDE_TAPC_DEFS
`include "scr1_arch_description.svh"
`ifdef SCR1_DBG_EN
//==============================================================================
// Parameters
//==============================================================================
localparam int unsigned SCR1_TAP_STATE_WIDTH = 4;
localparam int unsigned SCR1_TAP_INSTRUCTION_WIDTH = 5;
localparam int unsigned SCR1_TAP_DR_IDCODE_WIDTH = 32;
localparam int unsigned SCR1_TAP_DR_BLD_ID_WIDTH = 32;
localparam int unsigned SCR1_TAP_DR_BYPASS_WIDTH = 1;
//localparam bit [SCR1_TAP_DR_IDCODE_WIDTH-1:0] SCR1_TAP_IDCODE_RISCV_SC = `SCR1_TAP_IDCODE;
localparam bit [SCR1_TAP_DR_BLD_ID_WIDTH-1:0] SCR1_TAP_BLD_ID_VALUE = `SCR1_MIMPID;
//==============================================================================
// Types
//==============================================================================
typedef enum logic [SCR1_TAP_STATE_WIDTH-1:0] {
SCR1_TAP_STATE_RESET,
SCR1_TAP_STATE_IDLE,
SCR1_TAP_STATE_DR_SEL_SCAN,
SCR1_TAP_STATE_DR_CAPTURE,
SCR1_TAP_STATE_DR_SHIFT,
SCR1_TAP_STATE_DR_EXIT1,
SCR1_TAP_STATE_DR_PAUSE,
SCR1_TAP_STATE_DR_EXIT2,
SCR1_TAP_STATE_DR_UPDATE,
SCR1_TAP_STATE_IR_SEL_SCAN,
SCR1_TAP_STATE_IR_CAPTURE,
SCR1_TAP_STATE_IR_SHIFT,
SCR1_TAP_STATE_IR_EXIT1,
SCR1_TAP_STATE_IR_PAUSE,
SCR1_TAP_STATE_IR_EXIT2,
SCR1_TAP_STATE_IR_UPDATE
`ifdef SCR1_XPROP_EN
,
SCR1_TAP_STATE_XXX = 'X
`endif // SCR1_XPROP_EN
} type_scr1_tap_state_e;
typedef enum logic [SCR1_TAP_INSTRUCTION_WIDTH - 1:0] {
SCR1_TAP_INSTR_IDCODE = 5'h01,
SCR1_TAP_INSTR_BLD_ID = 5'h04,
SCR1_TAP_INSTR_SCU_ACCESS = 5'h09,
SCR1_TAP_INSTR_DTMCS = 5'h10,
SCR1_TAP_INSTR_DMI_ACCESS = 5'h11,
SCR1_TAP_INSTR_BYPASS = 5'h1F
`ifdef SCR1_XPROP_EN
,
SCR1_TAP_INSTR_XXX = 'X
`endif // SCR1_XPROP_EN
} type_scr1_tap_instr_e;
`endif // SCR1_DBG_EN
`endif // SCR1_INCLUDE_TAPC_DEFS

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/// Copyright by Syntacore LLC © 2016-2021. See LICENSE for details
/// @file <scr1_tdu.svh>
/// @brief Trigger Debug Module header
///
`ifndef SCR1_INCLUDE_TDU_DEFS
`define SCR1_INCLUDE_TDU_DEFS
//`include "scr1_arch_description.svh"
`ifdef SCR1_TDU_EN
//`include "scr1_csr.svh"
`include "scr1_arch_description.svh"
//`include "scr1_arch_types.svh"
`include "scr1_csr.svh"
parameter int unsigned SCR1_TDU_MTRIG_NUM = SCR1_TDU_TRIG_NUM;
`ifdef SCR1_TDU_ICOUNT_EN
parameter int unsigned SCR1_TDU_ALLTRIG_NUM = SCR1_TDU_MTRIG_NUM + 1'b1;
`else
parameter int unsigned SCR1_TDU_ALLTRIG_NUM = SCR1_TDU_MTRIG_NUM;
`endif
parameter int unsigned SCR1_TDU_ADDR_W = `SCR1_XLEN;
parameter int unsigned SCR1_TDU_DATA_W = `SCR1_XLEN;
// Register map
parameter SCR1_CSR_ADDR_TDU_OFFS_W = 3;
parameter bit [SCR1_CSR_ADDR_TDU_OFFS_W-1:0] SCR1_CSR_ADDR_TDU_OFFS_TSELECT = SCR1_CSR_ADDR_TDU_OFFS_W'(0);
parameter bit [SCR1_CSR_ADDR_TDU_OFFS_W-1:0] SCR1_CSR_ADDR_TDU_OFFS_TDATA1 = SCR1_CSR_ADDR_TDU_OFFS_W'(1);
parameter bit [SCR1_CSR_ADDR_TDU_OFFS_W-1:0] SCR1_CSR_ADDR_TDU_OFFS_TDATA2 = SCR1_CSR_ADDR_TDU_OFFS_W'(2);
parameter bit [SCR1_CSR_ADDR_TDU_OFFS_W-1:0] SCR1_CSR_ADDR_TDU_OFFS_TINFO = SCR1_CSR_ADDR_TDU_OFFS_W'(4);
parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_TDU_TSELECT = SCR1_CSR_ADDR_TDU_MBASE + SCR1_CSR_ADDR_TDU_OFFS_TSELECT;
parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_TDU_TDATA1 = SCR1_CSR_ADDR_TDU_MBASE + SCR1_CSR_ADDR_TDU_OFFS_TDATA1;
parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_TDU_TDATA2 = SCR1_CSR_ADDR_TDU_MBASE + SCR1_CSR_ADDR_TDU_OFFS_TDATA2;
parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_TDU_TINFO = SCR1_CSR_ADDR_TDU_MBASE + SCR1_CSR_ADDR_TDU_OFFS_TINFO;
// TDATA1
parameter int unsigned SCR1_TDU_TDATA1_TYPE_HI = `SCR1_XLEN-1;
parameter int unsigned SCR1_TDU_TDATA1_TYPE_LO = `SCR1_XLEN-4;
parameter int unsigned SCR1_TDU_TDATA1_DMODE = `SCR1_XLEN-5;
// TDATA1: constant bits values
parameter bit SCR1_TDU_TDATA1_DMODE_VAL = 1'b0;
// MCONTROL: bits number
parameter int unsigned SCR1_TDU_MCONTROL_MASKMAX_HI = `SCR1_XLEN-6;
parameter int unsigned SCR1_TDU_MCONTROL_MASKMAX_LO = `SCR1_XLEN-11;
parameter int unsigned SCR1_TDU_MCONTROL_RESERVEDB_HI = `SCR1_XLEN-12;
parameter int unsigned SCR1_TDU_MCONTROL_RESERVEDB_LO = 21;
parameter int unsigned SCR1_TDU_MCONTROL_HIT = 20;
parameter int unsigned SCR1_TDU_MCONTROL_SELECT = 19;
parameter int unsigned SCR1_TDU_MCONTROL_TIMING = 18;
parameter int unsigned SCR1_TDU_MCONTROL_ACTION_HI = 17;
parameter int unsigned SCR1_TDU_MCONTROL_ACTION_LO = 12;
parameter int unsigned SCR1_TDU_MCONTROL_CHAIN = 11;
parameter int unsigned SCR1_TDU_MCONTROL_MATCH_HI = 10;
parameter int unsigned SCR1_TDU_MCONTROL_MATCH_LO = 7;
parameter int unsigned SCR1_TDU_MCONTROL_M = 6;
parameter int unsigned SCR1_TDU_MCONTROL_RESERVEDA = 5;
parameter int unsigned SCR1_TDU_MCONTROL_S = 4;
parameter int unsigned SCR1_TDU_MCONTROL_U = 3;
parameter int unsigned SCR1_TDU_MCONTROL_EXECUTE = 2;
parameter int unsigned SCR1_TDU_MCONTROL_STORE = 1;
parameter int unsigned SCR1_TDU_MCONTROL_LOAD = 0;
// MCONTROL: constant bits values
parameter bit [SCR1_TDU_TDATA1_TYPE_HI-SCR1_TDU_TDATA1_TYPE_LO:0]
SCR1_TDU_MCONTROL_TYPE_VAL = 2'd2;
parameter bit SCR1_TDU_MCONTROL_SELECT_VAL = 1'b0;
parameter bit SCR1_TDU_MCONTROL_TIMING_VAL = 1'b0;
parameter bit [SCR1_TDU_MCONTROL_MASKMAX_HI-SCR1_TDU_MCONTROL_MASKMAX_LO:0]
SCR1_TDU_MCONTROL_MASKMAX_VAL = 1'b0;
parameter bit SCR1_TDU_MCONTROL_RESERVEDA_VAL = 1'b0;
// ICOUNT: bits number
parameter int unsigned SCR1_TDU_ICOUNT_DMODE = `SCR1_XLEN-5;
parameter int unsigned SCR1_TDU_ICOUNT_RESERVEDB_HI = `SCR1_XLEN-6;
parameter int unsigned SCR1_TDU_ICOUNT_RESERVEDB_LO = 25;
parameter int unsigned SCR1_TDU_ICOUNT_HIT = 24;
parameter int unsigned SCR1_TDU_ICOUNT_COUNT_HI = 23;
parameter int unsigned SCR1_TDU_ICOUNT_COUNT_LO = 10;
parameter int unsigned SCR1_TDU_ICOUNT_M = 9;
parameter int unsigned SCR1_TDU_ICOUNT_RESERVEDA = 8;
parameter int unsigned SCR1_TDU_ICOUNT_S = 7;
parameter int unsigned SCR1_TDU_ICOUNT_U = 6;
parameter int unsigned SCR1_TDU_ICOUNT_ACTION_HI = 5;
parameter int unsigned SCR1_TDU_ICOUNT_ACTION_LO = 0;
// ICOUNT: constant bits values
parameter bit [SCR1_TDU_TDATA1_TYPE_HI-SCR1_TDU_TDATA1_TYPE_LO:0]
SCR1_TDU_ICOUNT_TYPE_VAL = 2'd3;
parameter bit [SCR1_TDU_ICOUNT_RESERVEDB_HI-SCR1_TDU_ICOUNT_RESERVEDB_LO:0]
SCR1_TDU_ICOUNT_RESERVEDB_VAL = 1'b0;
parameter bit SCR1_TDU_ICOUNT_RESERVEDA_VAL = 1'b0;
// CPU pipeline monitors
typedef struct packed {
logic vd;
logic req;
logic [`SCR1_XLEN-1:0] addr;
} type_scr1_brkm_instr_mon_s;
typedef struct packed {
logic vd;
logic load;
logic store;
logic [`SCR1_XLEN-1:0] addr;
} type_scr1_brkm_lsu_mon_s;
`endif // SCR1_TDU_EN
`endif // SCR1_INCLUDE_TDU_DEFS