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This commit is contained in:
Mikhail Yenuchenko
2026-01-20 16:23:00 +03:00
commit c8ab0ca4f7
107 changed files with 285173 additions and 0 deletions
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199
sim/tests/riscv_compliance/Makefile Normal file
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## @file
## Syntacore SCR* tests
##
## @copyright 2015-2018 Syntacore. All rights reserved.
## RISCV-Compliance
##
ARCH ?=im
override ARCH:=rv32$(ARCH)
src_dir := $(CURDIR)
RISCV_COMPLIANCE_TESTS := $(src_dir)/../../../dependencies/riscv-compliance/
#I IM IMC IC
#EM EMC EC
ifeq (rv32e,$(findstring rv32e,$(ARCH)))
$(info >>> RV32E - no compliance tests)
else ## ifdef SCR_BASE_RVE_EXT
#ifeq (rv32i,$(findstring rv32i,$(ARCH)))
ifeq ($(ARCH),$(filter $(ARCH),rv32i rv32im rv32imc rv32ic))
$(info >>> I32 TESTS)
included_i += $(filter %.S,\
$(wildcard $(RISCV_COMPLIANCE_TESTS)/riscv-test-suite/rv32i/src/*))
included_i += $(filter %.S,\
$(wildcard $(RISCV_COMPLIANCE_TESTS)/riscv-test-suite/rv32Zicsr/src/*))
included_i += $(filter %.S,\
$(wildcard $(RISCV_COMPLIANCE_TESTS)/riscv-test-suite/rv32Zifencei/src/*))
compliance_set += $(included_i)
endif
#$(if or ifeq(rv32im,$(findstring rv32im,$(ARCH))), (rv32imc,$(findstring rv32imc,$(ARCH))))
ifeq ($(ARCH),$(filter $(ARCH), rv32im rv32imc))
$(info >>> IM32 TESTS)
included_im += $(filter %.S,\
$(wildcard $(RISCV_COMPLIANCE_TESTS)/riscv-test-suite/rv32im/src/*))
compliance_set += $(included_im)
endif ##
ifeq (rv32imc,$(findstring rv32imc,$(ARCH)))
$(info >>> IMC32 TESTS)
included_imc += $(filter %.S,\
$(wildcard $(RISCV_COMPLIANCE_TESTS)/riscv-test-suite/rv32imc/src/*))
compliance_set += $(included_imc)
endif ## ifeq (rv32imc,$(findstring rv32imc,$(ARCH)))
ifeq (rv32ic,$(findstring rv32ic,$(ARCH)))
endif
endif ##
$(info >>>$(ARCH) set included)
ifeq ($(compliance_set),)
$(info >>> No compliance tests included)
endif
$(info >>>>> compliance set: $(compliance_set))
dst_dir := $(bld_dir)
test_name := riscv_compliance
bld_dir := $(addprefix $(dst_dir)/, $(test_name))
obj_dir := $(bld_dir)/riscv_compliance_objs
#cut_list += scall csr shamt simple
cut_list += I-MISALIGN_JMP-01 I-MISALIGN_LDST-01 I-EBREAK-01 I-ECALL-01
reference_src += $(wildcard $(RISCV_COMPLIANCE_TESTS)/riscv-test-suite/rv32i*/*/*.reference_output)
reference_src += $(wildcard $(RISCV_COMPLIANCE_TESTS)/riscv-test-suite/rv32Zi*/*/*.reference_output)
testnames := $(basename $(notdir $(compliance_set)))
filtered := $(filter-out $(cut_list),$(testnames))
objs := $(addprefix $(bld_dir)/,$(filtered:%=%.o))
test_elf := $(addprefix $(dst_dir)/compliance_,$(filtered:%=%.elf))
test_hex := $(addprefix $(dst_dir)/compliance_,$(filtered:%=%.hex))
test_dump := $(addprefix $(bld_dir)/compliance_,$(filtered:%=%.dump))
compliance_macros_file := $(root_dir)/sim/tests/riscv_compliance/compliance_io.h
compliance_output ?= true
testnames_i := $(basename $(notdir $(included_i)))
testnames_im := $(basename $(notdir $(included_im)))
testnames_imc := $(basename $(notdir $(included_imc)))
filtered_i := $(filter-out $(cut_list),$(testnames_i))
filtered_im := $(filter-out $(cut_list),$(testnames_im))
filtered_imc := $(filter-out $(cut_list),$(testnames_imc))
# ARCH_FLAGS := -Wa,-march=rv32im -march=rv32im
# ARCH_FLAGS_C := -Wa,-march=rv32imc -march=rv32imc
CFLAGS := -I$(inc_dir) -I$(src_dir) -DASM -mabi=ilp32 -D__riscv_xlen=32 -w
LDFLAGS := -static -fvisibility=hidden -nostdlib -nostartfiles -T$(inc_dir)/link.ld -march=$(ARCH)_zicsr_zifencei -mabi=ilp32
GCCVERSIONGT7 := $(shell expr `$(RISCV_GCC) -dumpfullversion | cut -f1 -d'.'` \> 7)
ifeq "$(GCCVERSIONGT7)" "1"
LDFLAGS += -mno-relax
endif
VPATH += $(src_dir) $(bld_dir) $(obj_dir) $(asm_path) $(ref_path) $(RISCV_COMPLIANCE_TESTS)
ifeq ($(compliance_output), true)
CFLAGS += -D_COMPLIANCE_OUTPUT
endif
default: clean log_requested_tgt check_version cp_asm ref_data $(test_elf) $(test_hex) $(test_dump)
define compile_template
$(obj_dir)/$(1).o: $(obj_dir) cp_asm
$(RISCV_GCC) -c $$(bld_dir)/compliance_asm/$(1).S $$(CFLAGS) -Wa,$(2) $(2) -o $$@
endef
define preprocessing
for test_asm in $(1); do \
march_tmp=$$test_asm ; \
march_tmp=$${march_tmp%/src*} ; \
march_tmp=$$(basename $$march_tmp) ; \
file_name="$$(basename $${test_asm})" ; \
$(RISCV_GCC) $(CFLAGS) -Wa,$(2) $(2) -E $$test_asm \
-o $(bld_dir)/compliance_asm/$$file_name ; \
done
endef
$(foreach SRC,$(filtered_i),$(eval $(call compile_template,$(SRC),-march=rv32i_zicsr_zifencei)))
$(foreach SRC,$(filtered_im),$(eval $(call compile_template,$(SRC),-march=rv32im_zicsr_zifencei)))
$(foreach SRC,$(filtered_imc),$(eval $(call compile_template,$(SRC),-march=rv32imc_zicsr_zifencei)))
log_requested_tgt: $(bld_dir)
$(foreach test_name, $(filtered), $(eval $(shell echo compliance_$(test_name).hex >> $(bld_dir)/../test_info)))
$(bld_dir) :
mkdir -p $(bld_dir)
$(obj_dir) : | ref_data
mkdir -p $(obj_dir)
$(dst_dir)/compliance_%.elf: $(obj_dir)/%.o | $(dep_files)
$(RISCV_GCC) $^ $(LDFLAGS) -o $@ -g
$(dst_dir)/compliance_%.hex: $(dst_dir)/compliance_%.elf
$(RISCV_OBJCOPY) $^ $@
$(bld_dir)/compliance_%.dump: $(dst_dir)/compliance_%.elf
$(RISCV_OBJDUMP) -D -w -x -S $^ > $@
ref_data:
mkdir -p $(bld_dir)/ref_data
for files in $(reference_src) ; do \
sed_input=$$files ; \
sed_output=$$(basename $${files%.*}) ; \
sed "s/\r$$//; \
s/\(........\)/\1,/g; \
s/.$$//; s/\(.*\),\(.*\),\(.*\),\(.*\)/\4,\3,\2,\1/;" \
$$sed_input > $(bld_dir)/ref_data/$$sed_output; \
done
cp_asm:
mkdir -p $(bld_dir)/compliance_asm
$(call preprocessing,$(included_i),-march=rv32i_zicsr_zifencei)
$(call preprocessing,$(included_im),-march=rv32im_zicsr_zifencei)
$(call preprocessing,$(included_imc),-march=rv32imc_zicsr_zifencei)
riscv_compliance_tests_dir := $(if $(RISCV_COMPLIANCE_TESTS), $(RISCV_COMPLIANCE_TESTS), ./undefined)
riscv_tests_commit := d51259b2a949be3af02e776c39e135402675ac9b
## commit hash readed from local copy of https://github.com/riscv/riscv-compliance
tmp_commit = $(shell cd $(riscv_compliance_tests_dir) 2>/dev/null && git log -1 | grep "commit" | cut -f2 -d ' ')
is_commit_good = $(if $(subst $(riscv_tests_commit),,$(tmp_commit)),false,true)
# Color
RED=\033[0;31m
NC=\033[0m
check_version : $(riscv_compliance_tests_dir)
@if [ ! -d $(riscv_compliance_tests_dir) ]; then \
echo -e "$(RED)==========================================================================" &&\
echo " Error! Environment variable RISCV_COMPLIANCE_TESTS='$(riscv_compliance_tests_dir)' " &&\
echo " directory not exist!" && \
echo "==========================================================================$(NC)" ; \
fi
ifneq ($(is_commit_good),true)
@echo -e "$(RED)=========================================================================="
@echo " Warning! Execution of test code is not guaranteed "
@echo " while using the current commit of repository located at : $(riscv_compliance_tests_dir) ."
@echo " "
@echo " riscv_compliance repository must point to commit $(riscv_tests_commit)!"
@echo -e "==========================================================================$(NC)"
endif
$(riscv_compliance_tests_dir) :.
ifndef RISCV_COMPLIANCE_TESTS
@echo -e "$(RED)=========================================================================="
@echo " Error! Environment variable RISCV_COMPLIANCE_TESTS not set!"
@echo " You must set the environment variable RISCV_COMPLIANCE_TESTS"
@echo " The variable should point to the local copy of the"
@echo " repository https://github.com/riscv/riscv-compliance"
@echo " with the commit $(riscv_tests_commit)"
@echo -e "==========================================================================$(NC)"
exit 1
endif
clean:
$(RM) -R $(test_elf) $(test_hex) $(bld_dir)
.PHONY: check_version clean ref_data cp_asm default

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sim/tests/riscv_compliance/aw_test_macros.h Normal file
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/*
COPY OF /riscv-compliance/riscv-test-env/aw_test_macros.h
*/
// See LICENSE for license details.
#ifndef __TEST_MACROS_SCALAR_H
#define __TEST_MACROS_SCALAR_H
#-----------------------------------------------------------------------
# Helper macros
#-----------------------------------------------------------------------
#define MASK_XLEN(x) ((x) & ((1 << (__riscv_xlen - 1) << 1) - 1))
#define CHECK_XLEN li a0, 1; slli a0, a0, 31; bltz a0, 1f; RVTEST_PASS; 1: srli a0, a0, 31; la t0, begin_signature; sw a0, 0(t0)
#define TESTNUM gp
#define SWSIG( testnum, testreg ) \
la x28, test_res; \
sw testreg, (testnum<<2)(x28); \
#
# Address = base+(testnum<<2)
# sw testreg, (testnum<<2)(basereg)
#
#define TEST_CASE( testnum, testreg, correctval, code... ) \
test_ ## testnum: \
code; \
li x29, MASK_XLEN(correctval); \
li TESTNUM, testnum; \
SWSIG(testnum,testreg); \
bne testreg, x29, fail;
# We use a macro hack to simpify code generation for various numbers
# of bubble cycles.
#define TEST_INSERT_NOPS_0
#define TEST_INSERT_NOPS_1 nop; TEST_INSERT_NOPS_0
#define TEST_INSERT_NOPS_2 nop; TEST_INSERT_NOPS_1
#define TEST_INSERT_NOPS_3 nop; TEST_INSERT_NOPS_2
#define TEST_INSERT_NOPS_4 nop; TEST_INSERT_NOPS_3
#define TEST_INSERT_NOPS_5 nop; TEST_INSERT_NOPS_4
#define TEST_INSERT_NOPS_6 nop; TEST_INSERT_NOPS_5
#define TEST_INSERT_NOPS_7 nop; TEST_INSERT_NOPS_6
#define TEST_INSERT_NOPS_8 nop; TEST_INSERT_NOPS_7
#define TEST_INSERT_NOPS_9 nop; TEST_INSERT_NOPS_8
#define TEST_INSERT_NOPS_10 nop; TEST_INSERT_NOPS_9
#-----------------------------------------------------------------------
# RV64UI MACROS
#-----------------------------------------------------------------------
#-----------------------------------------------------------------------
# Tests for instructions with immediate operand
#-----------------------------------------------------------------------
#define SEXT_IMM(x) ((x) | (-(((x) >> 11) & 1) << 11))
#define TEST_IMM_OP( testnum, inst, result, val1, imm ) \
TEST_CASE( testnum, x30, result, \
li x1, MASK_XLEN(val1); \
inst x30, x1, SEXT_IMM(imm); \
)
#define TEST_IMM_SRC1_EQ_DEST( testnum, inst, result, val1, imm ) \
TEST_CASE( testnum, x1, result, \
li x1, MASK_XLEN(val1); \
inst x1, x1, SEXT_IMM(imm); \
)
#define TEST_IMM_DEST_BYPASS( testnum, nop_cycles, inst, result, val1, imm ) \
TEST_CASE( testnum, x6, result, \
li x4, 0; \
1: li x1, MASK_XLEN(val1); \
inst x30, x1, SEXT_IMM(imm); \
TEST_INSERT_NOPS_ ## nop_cycles \
addi x6, x30, 0; \
addi x4, x4, 1; \
li x5, 2; \
bne x4, x5, 1b \
)
#define TEST_IMM_SRC1_BYPASS( testnum, nop_cycles, inst, result, val1, imm ) \
TEST_CASE( testnum, x30, result, \
li x4, 0; \
1: li x1, MASK_XLEN(val1); \
TEST_INSERT_NOPS_ ## nop_cycles \
inst x30, x1, SEXT_IMM(imm); \
addi x4, x4, 1; \
li x5, 2; \
bne x4, x5, 1b \
)
#define TEST_IMM_ZEROSRC1( testnum, inst, result, imm ) \
TEST_CASE( testnum, x1, result, \
inst x1, x0, SEXT_IMM(imm); \
)
#define TEST_IMM_ZERODEST( testnum, inst, val1, imm ) \
TEST_CASE( testnum, x0, 0, \
li x1, MASK_XLEN(val1); \
inst x0, x1, SEXT_IMM(imm); \
)
#-----------------------------------------------------------------------
# Tests for an instruction with register operands
#-----------------------------------------------------------------------
#define TEST_R_OP( testnum, inst, result, val1 ) \
TEST_CASE( testnum, x30, result, \
li x1, val1; \
inst x30, x1; \
)
#define TEST_R_SRC1_EQ_DEST( testnum, inst, result, val1 ) \
TEST_CASE( testnum, x1, result, \
li x1, val1; \
inst x1, x1; \
)
#define TEST_R_DEST_BYPASS( testnum, nop_cycles, inst, result, val1 ) \
TEST_CASE( testnum, x6, result, \
li x4, 0; \
1: li x1, val1; \
inst x30, x1; \
TEST_INSERT_NOPS_ ## nop_cycles \
addi x6, x30, 0; \
addi x4, x4, 1; \
li x5, 2; \
bne x4, x5, 1b \
)
#-----------------------------------------------------------------------
# Tests for an instruction with register-register operands
#-----------------------------------------------------------------------
#define TEST_RR_OP( testnum, inst, result, val1, val2 ) \
TEST_CASE( testnum, x30, result, \
li x1, MASK_XLEN(val1); \
li x2, MASK_XLEN(val2); \
inst x30, x1, x2; \
)
#define TEST_RR_SRC1_EQ_DEST( testnum, inst, result, val1, val2 ) \
TEST_CASE( testnum, x1, result, \
li x1, MASK_XLEN(val1); \
li x2, MASK_XLEN(val2); \
inst x1, x1, x2; \
)
#define TEST_RR_SRC2_EQ_DEST( testnum, inst, result, val1, val2 ) \
TEST_CASE( testnum, x2, result, \
li x1, MASK_XLEN(val1); \
li x2, MASK_XLEN(val2); \
inst x2, x1, x2; \
)
#define TEST_RR_SRC12_EQ_DEST( testnum, inst, result, val1 ) \
TEST_CASE( testnum, x1, result, \
li x1, MASK_XLEN(val1); \
inst x1, x1, x1; \
)
#define TEST_RR_DEST_BYPASS( testnum, nop_cycles, inst, result, val1, val2 ) \
TEST_CASE( testnum, x6, result, \
li x4, 0; \
1: li x1, MASK_XLEN(val1); \
li x2, MASK_XLEN(val2); \
inst x30, x1, x2; \
TEST_INSERT_NOPS_ ## nop_cycles \
addi x6, x30, 0; \
addi x4, x4, 1; \
li x5, 2; \
bne x4, x5, 1b \
)
#define TEST_RR_SRC12_BYPASS( testnum, src1_nops, src2_nops, inst, result, val1, val2 ) \
TEST_CASE( testnum, x30, result, \
li x4, 0; \
1: li x1, MASK_XLEN(val1); \
TEST_INSERT_NOPS_ ## src1_nops \
li x2, MASK_XLEN(val2); \
TEST_INSERT_NOPS_ ## src2_nops \
inst x30, x1, x2; \
addi x4, x4, 1; \
li x5, 2; \
bne x4, x5, 1b \
)
#define TEST_RR_SRC21_BYPASS( testnum, src1_nops, src2_nops, inst, result, val1, val2 ) \
TEST_CASE( testnum, x30, result, \
li x4, 0; \
1: li x2, MASK_XLEN(val2); \
TEST_INSERT_NOPS_ ## src1_nops \
li x1, MASK_XLEN(val1); \
TEST_INSERT_NOPS_ ## src2_nops \
inst x30, x1, x2; \
addi x4, x4, 1; \
li x5, 2; \
bne x4, x5, 1b \
)
#define TEST_RR_ZEROSRC1( testnum, inst, result, val ) \
TEST_CASE( testnum, x2, result, \
li x1, MASK_XLEN(val); \
inst x2, x0, x1; \
)
#define TEST_RR_ZEROSRC2( testnum, inst, result, val ) \
TEST_CASE( testnum, x2, result, \
li x1, MASK_XLEN(val); \
inst x2, x1, x0; \
)
#define TEST_RR_ZEROSRC12( testnum, inst, result ) \
TEST_CASE( testnum, x1, result, \
inst x1, x0, x0; \
)
#define TEST_RR_ZERODEST( testnum, inst, val1, val2 ) \
TEST_CASE( testnum, x0, 0, \
li x1, MASK_XLEN(val1); \
li x2, MASK_XLEN(val2); \
inst x0, x1, x2; \
)
#-----------------------------------------------------------------------
# Test memory instructions
#-----------------------------------------------------------------------
#define TEST_LD_OP( testnum, inst, result, offset, base ) \
TEST_CASE( testnum, x30, result, \
la x1, base; \
inst x30, offset(x1); \
)
#define TEST_ST_OP( testnum, load_inst, store_inst, result, offset, base ) \
TEST_CASE( testnum, x30, result, \
la x1, base; \
li x2, result; \
store_inst x2, offset(x1); \
load_inst x30, offset(x1); \
)
#define TEST_LD_DEST_BYPASS( testnum, nop_cycles, inst, result, offset, base ) \
test_ ## testnum: \
li TESTNUM, testnum; \
SWSIG (testnum, TESTNUM);\
li x4, 0; \
1: la x1, base; \
inst x30, offset(x1); \
TEST_INSERT_NOPS_ ## nop_cycles \
addi x6, x30, 0; \
li x29, result; \
bne x6, x29, fail; \
addi x4, x4, 1; \
li x5, 2; \
bne x4, x5, 1b; \
#define TEST_LD_SRC1_BYPASS( testnum, nop_cycles, inst, result, offset, base ) \
test_ ## testnum: \
li TESTNUM, testnum; \
SWSIG (testnum, TESTNUM);\
li x4, 0; \
1: la x1, base; \
TEST_INSERT_NOPS_ ## nop_cycles \
inst x30, offset(x1); \
li x29, result; \
bne x30, x29, fail; \
addi x4, x4, 1; \
li x5, 2; \
bne x4, x5, 1b \
#define TEST_ST_SRC12_BYPASS( testnum, src1_nops, src2_nops, load_inst, store_inst, result, offset, base ) \
test_ ## testnum: \
li TESTNUM, testnum; \
SWSIG (testnum, TESTNUM);\
li x4, 0; \
1: li x1, result; \
TEST_INSERT_NOPS_ ## src1_nops \
la x2, base; \
TEST_INSERT_NOPS_ ## src2_nops \
store_inst x1, offset(x2); \
load_inst x30, offset(x2); \
li x29, result; \
bne x30, x29, fail; \
addi x4, x4, 1; \
li x5, 2; \
bne x4, x5, 1b \
#define TEST_ST_SRC21_BYPASS( testnum, src1_nops, src2_nops, load_inst, store_inst, result, offset, base ) \
test_ ## testnum: \
li TESTNUM, testnum; \
SWSIG (testnum, TESTNUM);\
li x4, 0; \
1: la x2, base; \
TEST_INSERT_NOPS_ ## src1_nops \
li x1, result; \
TEST_INSERT_NOPS_ ## src2_nops \
store_inst x1, offset(x2); \
load_inst x30, offset(x2); \
li x29, result; \
bne x30, x29, fail; \
addi x4, x4, 1; \
li x5, 2; \
bne x4, x5, 1b \
#define TEST_BR2_OP_TAKEN( testnum, inst, val1, val2 ) \
test_ ## testnum: \
li TESTNUM, testnum; \
SWSIG (testnum, TESTNUM);\
li x1, val1; \
li x2, val2; \
inst x1, x2, 2f; \
bne x0, TESTNUM, fail; \
1: bne x0, TESTNUM, 3f; \
2: inst x1, x2, 1b; \
bne x0, TESTNUM, fail; \
3:
#define TEST_BR2_OP_NOTTAKEN( testnum, inst, val1, val2 ) \
test_ ## testnum: \
li TESTNUM, testnum; \
SWSIG (testnum, TESTNUM);\
li x1, val1; \
li x2, val2; \
inst x1, x2, 1f; \
bne x0, TESTNUM, 2f; \
1: bne x0, TESTNUM, fail; \
2: inst x1, x2, 1b; \
3:
#define TEST_BR2_SRC12_BYPASS( testnum, src1_nops, src2_nops, inst, val1, val2 ) \
test_ ## testnum: \
li TESTNUM, testnum; \
SWSIG (testnum, TESTNUM);\
li x4, 0; \
1: li x1, val1; \
TEST_INSERT_NOPS_ ## src1_nops \
li x2, val2; \
TEST_INSERT_NOPS_ ## src2_nops \
inst x1, x2, fail; \
addi x4, x4, 1; \
li x5, 2; \
bne x4, x5, 1b \
#define TEST_BR2_SRC21_BYPASS( testnum, src1_nops, src2_nops, inst, val1, val2 ) \
test_ ## testnum: \
li TESTNUM, testnum; \
SWSIG (testnum, TESTNUM);\
li x4, 0; \
1: li x2, val2; \
TEST_INSERT_NOPS_ ## src1_nops \
li x1, val1; \
TEST_INSERT_NOPS_ ## src2_nops \
inst x1, x2, fail; \
addi x4, x4, 1; \
li x5, 2; \
bne x4, x5, 1b \
#-----------------------------------------------------------------------
# Test jump instructions
#-----------------------------------------------------------------------
#define TEST_JR_SRC1_BYPASS( testnum, nop_cycles, inst ) \
test_ ## testnum: \
li TESTNUM, testnum; \
SWSIG (testnum, TESTNUM);\
li x4, 0; \
1: la x6, 2f; \
TEST_INSERT_NOPS_ ## nop_cycles \
inst x6; \
bne x0, TESTNUM, fail; \
2: addi x4, x4, 1; \
li x5, 2; \
bne x4, x5, 1b \
#define TEST_JALR_SRC1_BYPASS( testnum, nop_cycles, inst ) \
test_ ## testnum: \
li TESTNUM, testnum; \
SWSIG (testnum, TESTNUM);\
li x4, 0; \
1: la x6, 2f; \
TEST_INSERT_NOPS_ ## nop_cycles \
inst x19, x6, 0; \
bne x0, TESTNUM, fail; \
2: addi x4, x4, 1; \
li x5, 2; \
bne x4, x5, 1b \
#-----------------------------------------------------------------------
# RV64UF MACROS
#-----------------------------------------------------------------------
#-----------------------------------------------------------------------
# Tests floating-point instructions
#-----------------------------------------------------------------------
#define qNaNf 0f:7fc00000
#define sNaNf 0f:7f800001
#define qNaN 0d:7ff8000000000000
#define sNaN 0d:7ff0000000000001
#define TEST_FP_OP_S_INTERNAL( testnum, flags, result, val1, val2, val3, code... ) \
test_ ## testnum: \
li TESTNUM, testnum; \
SWSIG (testnum, TESTNUM);\
la a0, test_ ## testnum ## _data ;\
flw f0, 0(a0); \
flw f1, 4(a0); \
flw f2, 8(a0); \
lw a3, 12(a0); \
code; \
fsflags a1, x0; \
li a2, flags; \
bne a0, a3, fail; \
bne a1, a2, fail; \
.pushsection .data; \
.align 2; \
test_ ## testnum ## _data: \
.float val1; \
.float val2; \
.float val3; \
.result; \
.popsection
#define TEST_FP_OP_D_INTERNAL( testnum, flags, result, val1, val2, val3, code... ) \
test_ ## testnum: \
li TESTNUM, testnum; \
SWSIG (testnum, TESTNUM);\
la a0, test_ ## testnum ## _data ;\
fld f0, 0(a0); \
fld f1, 8(a0); \
fld f2, 16(a0); \
ld a3, 24(a0); \
code; \
fsflags a1, x0; \
li a2, flags; \
bne a0, a3, fail; \
bne a1, a2, fail; \
.pushsection .data; \
.align 3; \
test_ ## testnum ## _data: \
.double val1; \
.double val2; \
.double val3; \
.result; \
.popsection
// TODO: assign a separate mem location for the comparison address?
#define TEST_FP_OP_D32_INTERNAL( testnum, flags, result, val1, val2, val3, code... ) \
test_ ## testnum: \
li TESTNUM, testnum; \
SWSIG (testnum, TESTNUM);\
la a0, test_ ## testnum ## _data ;\
fld f0, 0(a0); \
fld f1, 8(a0); \
fld f2, 16(a0); \
lw a3, 24(a0); \
lw t1, 28(a0); \
code; \
fsflags a1, x0; \
li a2, flags; \
bne a0, a3, fail; \
bne t1, t2, fail; \
bne a1, a2, fail; \
.pushsection .data; \
.align 3; \
test_ ## testnum ## _data: \
.double val1; \
.double val2; \
.double val3; \
.result; \
.popsection
#define TEST_FCVT_S_D32( testnum, result, val1 ) \
TEST_FP_OP_D32_INTERNAL( testnum, 0, double result, val1, 0.0, 0.0, \
fcvt.s.d f3, f0; fcvt.d.s f3, f3; fsd f3, 0(a0); lw t2, 4(a0); lw a0, 0(a0))
#define TEST_FCVT_S_D( testnum, result, val1 ) \
TEST_FP_OP_D_INTERNAL( testnum, 0, double result, val1, 0.0, 0.0, \
fcvt.s.d f3, f0; fcvt.d.s f3, f3; fmv.x.d a0, f3)
#define TEST_FCVT_D_S( testnum, result, val1 ) \
TEST_FP_OP_S_INTERNAL( testnum, 0, float result, val1, 0.0, 0.0, \
fcvt.d.s f3, f0; fcvt.s.d f3, f3; fmv.x.s a0, f3)
#define TEST_FP_OP1_S( testnum, inst, flags, result, val1 ) \
TEST_FP_OP_S_INTERNAL( testnum, flags, float result, val1, 0.0, 0.0, \
inst f3, f0; fmv.x.s a0, f3)
#define TEST_FP_OP1_D32( testnum, inst, flags, result, val1 ) \
TEST_FP_OP_D32_INTERNAL( testnum, flags, double result, val1, 0.0, 0.0, \
inst f3, f0; fsd f3, 0(a0); lw t2, 4(a0); lw a0, 0(a0))
// ^: store computation result in address from a0, load high-word into t2
#define TEST_FP_OP1_D( testnum, inst, flags, result, val1 ) \
TEST_FP_OP_D_INTERNAL( testnum, flags, double result, val1, 0.0, 0.0, \
inst f3, f0; fmv.x.d a0, f3)
#define TEST_FP_OP1_S_DWORD_RESULT( testnum, inst, flags, result, val1 ) \
TEST_FP_OP_S_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \
inst f3, f0; fmv.x.s a0, f3)
#define TEST_FP_OP1_D32_DWORD_RESULT( testnum, inst, flags, result, val1 ) \
TEST_FP_OP_D32_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \
inst f3, f0; fsd f3, 0(a0); lw t2, 4(a0); lw a0, 0(a0))
// ^: store computation result in address from a0, load high-word into t2
#define TEST_FP_OP1_D_DWORD_RESULT( testnum, inst, flags, result, val1 ) \
TEST_FP_OP_D_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \
inst f3, f0; fmv.x.d a0, f3)
#define TEST_FP_OP2_S( testnum, inst, flags, result, val1, val2 ) \
TEST_FP_OP_S_INTERNAL( testnum, flags, float result, val1, val2, 0.0, \
inst f3, f0, f1; fmv.x.s a0, f3)
#define TEST_FP_OP2_D32( testnum, inst, flags, result, val1, val2 ) \
TEST_FP_OP_D32_INTERNAL( testnum, flags, double result, val1, val2, 0.0, \
inst f3, f0, f1; fsd f3, 0(a0); lw t2, 4(a0); lw a0, 0(a0))
// ^: store computation result in address from a0, load high-word into t2
#define TEST_FP_OP2_D( testnum, inst, flags, result, val1, val2 ) \
TEST_FP_OP_D_INTERNAL( testnum, flags, double result, val1, val2, 0.0, \
inst f3, f0, f1; fmv.x.d a0, f3)
#define TEST_FP_OP3_S( testnum, inst, flags, result, val1, val2, val3 ) \
TEST_FP_OP_S_INTERNAL( testnum, flags, float result, val1, val2, val3, \
inst f3, f0, f1, f2; fmv.x.s a0, f3)
#define TEST_FP_OP3_D32( testnum, inst, flags, result, val1, val2, val3 ) \
TEST_FP_OP_D32_INTERNAL( testnum, flags, double result, val1, val2, val3, \
inst f3, f0, f1, f2; fsd f3, 0(a0); lw t2, 4(a0); lw a0, 0(a0))
// ^: store computation result in address from a0, load high-word into t2
#define TEST_FP_OP3_D( testnum, inst, flags, result, val1, val2, val3 ) \
TEST_FP_OP_D_INTERNAL( testnum, flags, double result, val1, val2, val3, \
inst f3, f0, f1, f2; fmv.x.d a0, f3)
#define TEST_FP_INT_OP_S( testnum, inst, flags, result, val1, rm ) \
TEST_FP_OP_S_INTERNAL( testnum, flags, word result, val1, 0.0, 0.0, \
inst a0, f0, rm)
#define TEST_FP_INT_OP_D32( testnum, inst, flags, result, val1, rm ) \
TEST_FP_OP_D32_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \
inst a0, f0, f1; li t2, 0)
#define TEST_FP_INT_OP_D( testnum, inst, flags, result, val1, rm ) \
TEST_FP_OP_D_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \
inst a0, f0, rm)
#define TEST_FP_CMP_OP_S( testnum, inst, flags, result, val1, val2 ) \
TEST_FP_OP_S_INTERNAL( testnum, flags, word result, val1, val2, 0.0, \
inst a0, f0, f1)
#define TEST_FP_CMP_OP_D32( testnum, inst, flags, result, val1, val2 ) \
TEST_FP_OP_D32_INTERNAL( testnum, flags, dword result, val1, val2, 0.0, \
inst a0, f0, f1; li t2, 0)
#define TEST_FP_CMP_OP_D( testnum, inst, flags, result, val1, val2 ) \
TEST_FP_OP_D_INTERNAL( testnum, flags, dword result, val1, val2, 0.0, \
inst a0, f0, f1)
#define TEST_FCLASS_S(testnum, correct, input) \
TEST_CASE(testnum, a0, correct, li a0, input; fmv.s.x fa0, a0; \
fclass.s a0, fa0)
#define TEST_FCLASS_D32(testnum, correct, input) \
TEST_CASE(testnum, a0, correct, \
la a0, test_ ## testnum ## _data ;\
fld fa0, 0(a0); \
fclass.d a0, fa0) \
.pushsection .data; \
.align 3; \
test_ ## testnum ## _data: \
.dword input; \
.popsection
#define TEST_FCLASS_D(testnum, correct, input) \
TEST_CASE(testnum, a0, correct, li a0, input; fmv.d.x fa0, a0; \
fclass.d a0, fa0)
#define TEST_INT_FP_OP_S( testnum, inst, result, val1 ) \
test_ ## testnum: \
li TESTNUM, testnum; \
SWSIG (testnum, TESTNUM);\
la a0, test_ ## testnum ## _data ;\
lw a3, 0(a0); \
li a0, val1; \
inst f0, a0; \
fsflags x0; \
fmv.x.s a0, f0; \
bne a0, a3, fail; \
.pushsection .data; \
.align 2; \
test_ ## testnum ## _data: \
.float result; \
.popsection
#define TEST_INT_FP_OP_D32( testnum, inst, result, val1 ) \
test_ ## testnum: \
li TESTNUM, testnum; \
SWSIG (testnum, TESTNUM);\
la a0, test_ ## testnum ## _data ;\
lw a3, 0(a0); \
lw a4, 4(a0); \
li a1, val1; \
inst f0, a1; \
\
fsd f0, 0(a0); \
lw a1, 4(a0); \
lw a0, 0(a0); \
\
fsflags x0; \
bne a0, a3, fail; \
bne a1, a4, fail; \
.pushsection .data; \
.align 3; \
test_ ## testnum ## _data: \
.double result; \
.popsection
#define TEST_INT_FP_OP_D( testnum, inst, result, val1 ) \
test_ ## testnum: \
li TESTNUM, testnum; \
SWSIG (testnum, TESTNUM);\
la a0, test_ ## testnum ## _data ;\
ld a3, 0(a0); \
li a0, val1; \
inst f0, a0; \
fsflags x0; \
fmv.x.d a0, f0; \
bne a0, a3, fail; \
.pushsection .data; \
.align 3; \
test_ ## testnum ## _data: \
.double result; \
.popsection
// We need some special handling here to allow 64-bit comparison in 32-bit arch
// TODO: find a better name and clean up when intended for general usage?
#define TEST_CASE_D32( testnum, testreg1, testreg2, correctval, code... ) \
test_ ## testnum: \
code; \
la x31, test_ ## testnum ## _data ; \
lw x29, 0(x31); \
lw x31, 4(x31); \
li TESTNUM, testnum; \
SWSIG (testnum, TESTNUM);\
bne testreg1, x29, fail;\
bne testreg2, x31, fail;\
.pushsection .data; \
.align 3; \
test_ ## testnum ## _data: \
.dword correctval; \
.popsection
// ^ x30 is used in some other macros, to avoid issues we use x31 for upper word
#-----------------------------------------------------------------------
# Pass and fail code (assumes test num is in TESTNUM)
#-----------------------------------------------------------------------
#define TEST_PASSFAIL \
bne x0, TESTNUM, pass; \
fail: \
RVTEST_FAIL; \
pass: \
RVTEST_PASS \
#-----------------------------------------------------------------------
# Test data section
#-----------------------------------------------------------------------
#define TEST_DATA
#endif

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// RISC-V Compliance IO Test Header File
/*
* Copyright (c) 2005-2018 Imperas Software Ltd., www.imperas.com
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
* either express or implied.
*
* See the License for the specific language governing permissions and
* limitations under the License.
*
*/
#ifndef _COMPLIANCE_IO_H
#define _COMPLIANCE_IO_H
//-----------------------------------------------------------------------
// RV IO Macros (Non functional)
//-----------------------------------------------------------------------
#ifdef _COMPLIANCE_OUTPUT
#define RVTEST_IO_PUSH(_SP) \
la _SP, begin_regstate; \
sw x3, 0(_SP); \
sw x4, 4(_SP); \
sw x5, 8(_SP);
#define RVTEST_IO_POP(_SP) \
la _SP, begin_regstate; \
lw x3, 0(_SP); \
lw x4, 4(_SP); \
lw x5, 8(_SP);
#define RVTEST_IO_WRITE_STR(_SP, _STR) \
.section .data.string; \
20001: \
.string _STR; \
.section .text; \
RVTEST_IO_PUSH(_SP) \
li x3, 0xF0000000; \
la x4, 20001b; \
2: lb x5, 0(x4); \
sb x5, 0(x3); \
beq x5, zero, 1f; \
add x4, x4, 1; \
j 2b; \
1: RVTEST_IO_POP(_SP)
#else // #ifdef _COMPLIANCE_OUTPUT
#define RVTEST_IO_WRITE_STR(_SP, _STR)
#endif // #end #ifdef _COMPLIANCE_OUTPUT
#define RVTEST_IO_INIT
#define RVTEST_IO_CHECK()
#define RVTEST_IO_ASSERT_GPR_EQ(_SP, _R, _I)
#define RVTEST_IO_ASSERT_SFPR_EQ(_F, _R, _I)
#define RVTEST_IO_ASSERT_DFPR_EQ(_D, _R, _I)
#define RVTEST_IO_ASSERT_EQ(_R, _I)
#endif // _COMPLIANCE_IO_H

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// RISC-V Compliance Test Header File
// Copyright (c) 2017, Codasip Ltd. All Rights Reserved.
// See LICENSE for license details.
//
// Description: Common header file for RV32I tests
#ifndef _COMPLIANCE_TEST_H
#define _COMPLIANCE_TEST_H
//-----------------------------------------------------------------------
// RV Compliance Macros
//-----------------------------------------------------------------------
#define RV_COMPLIANCE_HALT \
#define RV_COMPLIANCE_RV32M \
RVTEST_RV32M \
#define RV_COMPLIANCE_CODE_BEGIN \
RVTEST_CODE_BEGIN \
#define RV_COMPLIANCE_CODE_END \
RVTEST_CODE_END \
#define RV_COMPLIANCE_DATA_BEGIN \
RVTEST_DATA_BEGIN \
#define RV_COMPLIANCE_DATA_END \
RVTEST_DATA_END \
#endif

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#ifndef _RISCV_TEST_H
#define _RISCV_TEST_H
#include "test_macros.h"
#endif

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// RISC-V Compliance IO Test Header File
/*
* Copyright (c) 2005-2018 Imperas Software Ltd., www.imperas.com
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
* either express or implied.
*
* See the License for the specific language governing permissions and
* limitations under the License.
*
*/
#include "riscv_macros.h"
//
// In general the following registers are reserved
// ra, a0, t0, t1
// Additionally on an assertion violation, t1, t2 are overwritten
// x1, x10, x5, x6, x7 respectively
// Floating registers reserved
// f5
//
#define MASK_XLEN(x) ((x) & ((1 << (__riscv_xlen - 1) << 1) - 1))
#define SEXT_IMM(x) ((x) | (-(((x) >> 11) & 1) << 11))
// Base function for integer operations
#define TEST_CASE(testreg, destreg, correctval, swreg, offset, code... ) \
code; \
sw destreg, offset(swreg); \
RVTEST_IO_ASSERT_GPR_EQ(testreg, destreg, correctval) \
// Base functions for single precision floating point operations
#define TEST_CASE_FP(test_num, destreg, reg1, reg2, correctval, val1, val2, swreg, offset, code... ) \
la a0, test_ ## test_num ## _data; \
flw reg1, 0(a0); \
flw reg2, 4(a0); \
lw t1, 8(a0); \
code; \
fsw destreg, offset(swreg); \
RVTEST_IO_ASSERT_SFPR_EQ(destreg, t1, correctval) \
.pushsection .data; \
.align 3; \
test_ ## test_num ## _data: \
.float val1; \
.float val2; \
.word correctval; \
.popsection
#define TEST_CASE_FP_I(test_num, destreg, reg, correctval, val, swreg, offset, code... ) \
la a0, test_ ## test_num ## _data; \
lw t1, 0(a0); \
code; \
fsw destreg, offset(swreg); \
RVTEST_IO_ASSERT_SFPR_EQ(destreg, t1, correctval) \
.pushsection .data; \
.align 1; \
test_ ## test_num ## _data: \
.word correctval; \
.popsection
#define TEST_CASE_FP_I2(test_num, destreg, reg, correctval, val, swreg, offset, code... ) \
la a0, test_ ## test_num ## _data; \
flw reg, 0(a0); \
lw t1, 4(a0); \
code; \
sw destreg, offset(swreg); \
RVTEST_IO_ASSERT_GPR_EQ(x31, destreg, correctval) \
.pushsection .data; \
.align 2; \
test_ ## test_num ## _data: \
.float val; \
.word correctval; \
.popsection
#define TEST_CASE_FP_4REG(test_num, destreg, reg1, reg2, reg3, correctval, val1, val2, val3, swreg, offset, code... ) \
la a0, test_ ## test_num ## _data; \
flw reg1, 0(a0); \
flw reg2, 4(a0); \
flw reg3, 8(a0); \
lw t1, 12(a0); \
code; \
fsw destreg, offset(swreg); \
RVTEST_IO_ASSERT_SFPR_EQ(destreg, t1, correctval) \
.pushsection .data; \
.align 4; \
test_ ## test_num ## _data: \
.float val1; \
.float val2; \
.float val3; \
.word correctval; \
.popsection
#define TEST_CASE_FP_FMVXS(test_num, destreg, reg, correctval, val, swreg, offset, code... ) \
la a0, test_ ## test_num ## _data; \
flw reg, 0(a0); \
code; \
sw destreg, offset(swreg); \
RVTEST_IO_ASSERT_GPR_EQ(x31, destreg, correctval) \
.pushsection .data; \
.align 1; \
test_ ## test_num ## _data: \
.float val; \
.popsection
#define TEST_CASE_FP_FMVSX(test_num, destreg, reg, correctval, val, swreg, offset, code...) \
la a0, test_ ## test_num ## _data; \
li reg, val; \
code; \
fsw destreg, offset(swreg); \
lw a1, 0(a0); \
RVTEST_IO_ASSERT_SFPR_EQ(destreg, a1, correctval) \
.pushsection .data; \
.align 1; \
test_ ## test_num ## _data: \
.word correctval; \
.popsection
// Base functions for double precision floating point operations - rv32d
#define TEST_CASE_FPD(test_num, destreg, reg1, reg2, correctval, val1, val2, swreg, offset, code... ) \
la a0, test_ ## test_num ## _data; \
fld reg1, 0(a0); \
fld reg2, 8(a0); \
code; \
fsd destreg, offset(swreg); \
lw t1, 16(a0); \
lw t2, 20(a0); \
la a0, store_ ## test_num ## _data; \
fsd destreg, 0(a0); \
lw a1, 0(a0); \
lw a2, 4(a0); \
RVTEST_IO_ASSERT_DFPR_EQ(destreg, t2, t1, a2, a1, correctval) \
.pushsection .data; \
.align 3; \
test_ ## test_num ## _data: \
.double val1; \
.double val2; \
.dword correctval; \
.popsection; \
.pushsection .data; \
store_ ## test_num ## _data: \
.fill 1, 8, -1; \
.popsection
#define TEST_CASE_FPD_I(test_num, destreg, reg, correctval, val, swreg, offset, code... ) \
la a0, test_ ## test_num ## _data; \
code; \
fsd destreg, offset(swreg); \
lw t1, 0(a0); \
lw t2, 4(a0); \
la a0, store_ ## test_num ## _data; \
fsd destreg, 0(a0); \
lw a1, 0(a0); \
lw a2, 4(a0); \
RVTEST_IO_ASSERT_DFPR_EQ(destreg, t2, t1, a2, a1, correctval) \
.pushsection .data; \
.align 1; \
test_ ## test_num ## _data: \
.dword correctval; \
.popsection; \
store_ ## test_num ## _data: \
.fill 1, 8, -1; \
.popsection
#define TEST_CASE_FPD_I2(test_num, destreg, reg, correctval, val, swreg, offset, code... ) \
la a0, test_ ## test_num ## _data; \
fld reg, 0(a0); \
lw t1, 8(a0); \
code; \
sw destreg, offset(swreg); \
RVTEST_IO_ASSERT_GPR_EQ(x31, destreg, correctval) \
.pushsection .data; \
.align 2; \
test_ ## test_num ## _data: \
.double val; \
.word correctval; \
.popsection
#define TEST_CASE_FPD_4REG(test_num, destreg, reg1, reg2, reg3, correctval, val1, val2, val3, swreg, offset, code... ) \
la a0, test_ ## test_num ## _data; \
fld reg1, 0(a0); \
fld reg2, 8(a0); \
fld reg3, 16(a0); \
code; \
fsd destreg, offset(swreg); \
lw t1, 24(a0); \
lw t2, 28(a0); \
la a0, store_ ## test_num ## _data; \
fsd destreg, 0(a0); \
lw a1, 0(a0); \
lw a2, 4(a0); \
RVTEST_IO_ASSERT_DFPR_EQ(destreg, t2, t1, a2, a1, correctval) \
.pushsection .data; \
.align 4; \
test_ ## test_num ## _data: \
.double val1; \
.double val2; \
.double val3; \
.dword correctval; \
.popsection; \
.pushsection .data; \
store_ ## test_num ## _data: \
.fill 1, 8, -1; \
.popsection
//Tests for a instructions with register-register operand
#define TEST_RR_OP(inst, destreg, reg1, reg2, correctval, val1, val2, swreg, offset, testreg) \
TEST_CASE(testreg, destreg, correctval, swreg, offset, \
li reg1, MASK_XLEN(val1); \
li reg2, MASK_XLEN(val2); \
inst destreg, reg1, reg2; \
)
#define TEST_RR_SRC1( inst, destreg, reg, correctval, val1, val2, swreg, offset, testreg) \
TEST_CASE(testreg, destreg, correctval, swreg, offset, \
li destreg, MASK_XLEN(val1); \
li reg, MASK_XLEN(val2); \
inst destreg, destreg, reg; \
)
#define TEST_RR_SRC2( inst, destreg, reg, correctval, val1, val2, swreg, offset, testreg) \
TEST_CASE(testreg, destreg, correctval, swreg, offset, \
li reg, MASK_XLEN(val1); \
li destreg, MASK_XLEN(val2); \
inst destreg, reg, destreg; \
)
#define TEST_RR_SRC12( inst, destreg, correctval, val, swreg, offset, testreg) \
TEST_CASE(testreg, destreg, correctval, swreg, offset, \
li destreg, MASK_XLEN(val1); \
inst destreg, destreg, destreg; \
)
#define TEST_RR_ZERO1( inst, destreg, reg, correctval, val, swreg, offset, testreg) \
TEST_CASE(testreg, destreg, correctval, swreg, offset, \
li reg, MASK_XLEN(val); \
inst destreg, x0, reg; \
)
#define TEST_RR_ZERO2( inst, destreg, reg, correctval, val, swreg, offset, testreg) \
TEST_CASE(testreg, destreg, correctval, swreg, offset, \
li reg, MASK_XLEN(val); \
inst destreg, reg, x0; \
)
#define TEST_RR_ZERO12( inst, destreg, correctval, swreg, offset, testreg) \
TEST_CASE(testreg, destreg, correctval, swreg, offset, \
inst destreg, x0, x0; \
)
#define TEST_RR_ZERODEST( inst, reg1, reg2, val1, val2, swreg, offset, testreg) \
TEST_CASE(testreg, x0, 0, swreg, offset, \
li reg1, MASK_XLEN(val1); \
li reg2, MASK_XLEN(val2); \
inst x0, reg1, reg2; \
)
//Tests for a instructions with register-immediate operand
#define TEST_IMM_OP( inst, destreg, reg, correctval, val, imm, swreg, offset, testreg) \
TEST_CASE(testreg, destreg, correctval, swreg, offset, \
li reg, MASK_XLEN(val); \
inst destreg, reg, SEXT_IMM(imm); \
)
#define TEST_IMM_SRC( inst, destreg, correctval, val, imm, swreg, offset, testreg) \
TEST_CASE(testreg, destreg, correctval, swreg, offset, \
li destreg, MASK_XLEN(val); \
inst destreg, destreg, SEXT_IMM(imm); \
)
#define TEST_IMM_ZEROSRC( inst, destreg, correctval, imm, swreg, offset, testreg) \
TEST_CASE(testreg, destreg, correctval, swreg, offset, \
inst destreg, x0, SEXT_IMM(imm); \
)
#define TEST_IMM_ZERODEST( inst, reg, val, imm, swreg, offset, testreg) \
TEST_CASE(testreg, x0, 0, swreg, offset, \
li reg, MASK_XLEN(val); \
inst x0, reg, SEXT_IMM(imm); \
)
#define TEST_IMM_ONEREG( inst, destreg, correctval, imm, swreg, offset, testreg) \
TEST_CASE(testreg, destreg, correctval, swreg, offset, \
inst destreg, SEXT_IMM(imm); \
)
#define TEST_AUIPC(inst, destreg, correctval, imm, swreg, offset, testreg) \
TEST_CASE(testreg, destreg, correctval, swreg, offset, \
1: \
inst destreg, imm; \
la swreg, 1b; \
sub destreg, destreg, swreg; \
)
//Tests for a compressed instruction
#define TEST_CR_OP( inst, destreg, reg, correctval, val1, val2, swreg, offset, testreg) \
TEST_CASE(testreg, destreg, correctval, swreg, offset, \
li reg, MASK_XLEN(val1); \
li destreg, MASK_XLEN(val2); \
inst destreg, reg; \
)
#define TEST_CI_OP( inst, destreg, correctval, val, imm, swreg, offset, testreg) \
TEST_CASE(testreg, destreg, correctval, swreg, offset, \
li destreg, MASK_XLEN(val); \
inst destreg, imm; \
)
#define TEST_CI_OP_NOREG(inst, correctval, imm, swreg, offset, testreg) \
TEST_CASE(testreg,x0, correctval, swreg, offset, \
inst imm; \
)
//Tests for floating point instructions - single precision
#define TEST_FP_OP(test_num, inst, destreg, reg1, reg2, correctval, val1, val2, swreg, offset) \
TEST_CASE_FP(test_num, destreg, reg1, reg2, correctval, val1, val2, swreg, offset, \
inst destreg, reg1, reg2; \
)
#define TEST_FP_ONEREG(test_num, inst, destreg, reg, correctval, val, swreg, offset) \
TEST_CASE_FP(test_num, destreg, reg, reg, correctval, val, val, swreg, offset, \
inst destreg, reg; \
)
#define TEST_FP_4REG(test_num, inst, destreg, reg1, reg2, reg3, correctval, val1, val2, val3, swreg, offset) \
TEST_CASE_FP_4REG(test_num, destreg, reg1, reg2, reg3, correctval, val1, val2, val3, swreg, offset, \
inst destreg, reg1, reg2, reg3; \
)
#define TEST_FP_I(test_num, inst, destreg, reg, correctval, val, swreg, offset) \
TEST_CASE_FP_I(test_num, destreg, reg, correctval, val, swreg, offset, \
li reg, MASK_XLEN(val); \
inst destreg, reg; \
)
#define TEST_FP_I2(test_num, inst, destreg, reg, correctval, val, swreg, offset) \
TEST_CASE_FP_I2(test_num, destreg, reg, correctval, val, swreg, offset, \
inst destreg, reg; \
)
//Tests for floating point instructions - double precision
#define TEST_FPD_OP(test_num, inst, destreg, reg1, reg2, correctval, val1, val2, swreg, offset) \
TEST_CASE_FPD(test_num, destreg, reg1, reg2, correctval, val1, val2, swreg, offset, \
inst destreg, reg1, reg2; \
)
#define TEST_FPD_ONEREG(test_num, inst, destreg, reg, correctval, val, swreg, offset) \
TEST_CASE_FPD(test_num, destreg, reg, reg, correctval, val, val, swreg, offset, \
inst destreg, reg; \
)
#define TEST_FPD_4REG(test_num, inst, destreg, reg1, reg2, reg3, correctval, val1, val2, val3, swreg, offset) \
TEST_CASE_FPD_4REG(test_num, destreg, reg1, reg2, reg3, correctval, val1, val2, val3, swreg, offset, \
inst destreg, reg1, reg2, reg3; \
)
#define TEST_FPD_I(test_num, inst, destreg, reg, correctval, val, swreg, offset) \
TEST_CASE_FPD_I(test_num, destreg, reg, correctval, val, swreg, offset, \
li reg, MASK_XLEN(val); \
inst destreg, reg; \
)
#define TEST_FPD_I2(test_num, inst, destreg, reg, correctval, val, swreg, offset) \
TEST_CASE_FPD_I2(test_num, destreg, reg, correctval, val, swreg, offset, \
inst destreg, reg; \
)
#define TEST_CADDI16SP(correctval, imm, swreg, offset, testreg) \
TEST_CASE(testreg,x2, correctval, swreg, offset, \
c.addi16sp x2, imm; \
)
#define TEST_CADDI4SPN(destreg, correctval, imm, swreg, offset, testreg) \
TEST_CASE(testreg,destreg, correctval, swreg, offset, \
c.addi4spn destreg, x2, SEXT_IMM(imm); \
)
#define TEST_CJL(inst, reg, val, swreg, offset) \
li x10, val; \
la reg, 1f; \
inst reg; \
li x10, 0x123ab; \
1: \
sw x10, offset(swreg); \
RVTEST_IO_ASSERT_GPR_EQ(x31, x10, val); \
#define ABS(x) ((x >> 11) ^ x) - (x >> 11)
#define TEST_CJ(inst, reg, val, swreg, offset) \
li reg, val; \
inst 1f; \
li reg, 0x123ab; \
1: \
sw reg, offset(swreg); \
RVTEST_IO_ASSERT_GPR_EQ(x31, reg, val); \
#define TEST_CL(inst, reg, imm, swreg, offset) \
la reg, test_data; \
inst reg, imm(reg); \
sw reg, offset(swreg); \
// lw reg, imm(x2)
// c.lwsp reg, imm(x2)
#define TEST_CLWSP(reg, imm, swreg, offset) \
la x2, test_data; \
c.lwsp reg, imm(x2); \
sw reg, offset(swreg); \
#define TEST_CSW(test_data, inst, reg1, reg2, val, imm, swreg, offset) \
li reg1, val; \
la reg2, test_data; \
inst reg1, imm(reg2); \
lw reg1, imm(reg2); \
sw reg1, offset(swreg); \
RVTEST_IO_ASSERT_GPR_EQ(x31, reg1, val); \
#define TEST_CSWSP(test_data, reg, val, imm, swreg, offset) \
la x2, test_data; \
li reg, val; \
c.swsp reg, imm(x2); \
lw reg, imm(x2); \
sw reg, offset(swreg); \
RVTEST_IO_ASSERT_GPR_EQ(x31, reg, val); \
#define TEST_CBEQZ(reg, val, swreg, offset) \
li reg, val; \
c.sub reg, reg; \
c.beqz reg, 3f; \
li reg, 0x123ab; \
3: \
sw reg, offset(swreg); \
RVTEST_IO_ASSERT_GPR_EQ(x31, reg, 0x0); \
#define TEST_CBNEZ(reg, val, swreg, offset) \
li reg, val; \
c.bnez reg, 4f; \
li reg, 0x0; \
4: \
sw reg, offset(swreg); \
RVTEST_IO_ASSERT_GPR_EQ(x31, reg, val); \
#define TEST_FMVXS(test_num, destreg, reg, correctval, val, swreg, offset) \
TEST_CASE_FP_FMVXS(test_num, destreg, reg, correctval, val, swreg, offset, \
fmv.x.s destreg, reg; \
)
#define TEST_FMVSX(test_num, destreg, reg, correctval, val, swreg, offset) \
TEST_CASE_FP_FMVSX(test_num, destreg, reg, correctval, val, swreg, offset, \
fmv.s.x destreg, reg; \
)
#define SWSIG(a,b)

593
sim/tests/riscv_compliance/test_macros.h Normal file
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@@ -0,0 +1,593 @@
// RISC-V Compliance Test Header File
// Copyright (c) 2017, Codasip Ltd. All Rights Reserved.
// See LICENSE for license details.
//
// Description: Common header file for RV32I tests
#ifndef _TEST_MACROS_H
#define _TEST_MACROS_H
#include "riscv_macros.h"
// RISC-V Compliance IO Test Header File
/*
* Copyright (c) 2005-2018 Imperas Software Ltd., www.imperas.com
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
* either express or implied.
*
* See the License for the specific language governing permissions and
* limitations under the License.
*
*/
//
// In general the following registers are reserved
// ra, a0, t0, t1
// Additionally on an assertion violation, t1, t2 are overwritten
// x1, x10, x5, x6, x7 respectively
// Floating registers reserved
// f5
//
#define MASK_XLEN(x) ((x) & ((1 << (__riscv_xlen - 1) << 1) - 1))
#define SEXT_IMM(x) ((x) | (-(((x) >> 11) & 1) << 11))
// Base function for integer operations
#define TEST_CASE(destreg, correctval, swreg, offset, code... ) \
code; \
sw destreg, offset(swreg); \
RVTEST_IO_ASSERT_GPR_EQ(x31, destreg, correctval) \
// Base functions for single precision floating point operations
#define TEST_CASE_FP(test_num, destreg, reg1, reg2, correctval, val1, val2, swreg, offset, code... ) \
la a0, test_ ## test_num ## _data; \
flw reg1, 0(a0); \
flw reg2, 4(a0); \
lw t1, 8(a0); \
code; \
fsw destreg, offset(swreg); \
RVTEST_IO_ASSERT_SFPR_EQ(destreg, t1, correctval) \
.pushsection .data; \
.balign 8; \
test_ ## test_num ## _data: \
.float val1; \
.float val2; \
.word correctval; \
.popsection
#define TEST_CASE_FP_I(test_num, destreg, reg, correctval, val, swreg, offset, code... ) \
la a0, test_ ## test_num ## _data; \
lw t1, 0(a0); \
code; \
fsw destreg, offset(swreg); \
RVTEST_IO_ASSERT_SFPR_EQ(destreg, t1, correctval) \
.pushsection .data; \
.balign 2; \
test_ ## test_num ## _data: \
.word correctval; \
.popsection
#define TEST_CASE_FP_I2(test_num, destreg, reg, correctval, val, swreg, offset, code... ) \
la a0, test_ ## test_num ## _data; \
flw reg, 0(a0); \
lw t1, 4(a0); \
code; \
sw destreg, offset(swreg); \
RVTEST_IO_ASSERT_GPR_EQ(x31, destreg, correctval) \
.pushsection .data; \
.balign 4; \
test_ ## test_num ## _data: \
.float val; \
.word correctval; \
.popsection
#define TEST_CASE_FP_4REG(test_num, destreg, reg1, reg2, reg3, correctval, val1, val2, val3, swreg, offset, code... ) \
la a0, test_ ## test_num ## _data; \
flw reg1, 0(a0); \
flw reg2, 4(a0); \
flw reg3, 8(a0); \
lw t1, 12(a0); \
code; \
fsw destreg, offset(swreg); \
RVTEST_IO_ASSERT_SFPR_EQ(destreg, t1, correctval) \
.pushsection .data; \
.balign 16; \
test_ ## test_num ## _data: \
.float val1; \
.float val2; \
.float val3; \
.word correctval; \
.popsection
#define TEST_CASE_FP_FMVXS(test_num, destreg, reg, correctval, val, swreg, offset, code... ) \
la a0, test_ ## test_num ## _data; \
flw reg, 0(a0); \
code; \
sw destreg, offset(swreg); \
RVTEST_IO_ASSERT_GPR_EQ(x31, destreg, correctval) \
.pushsection .data; \
.balign 2; \
test_ ## test_num ## _data: \
.float val; \
.popsection
#define TEST_CASE_FP_FMVSX(test_num, destreg, reg, correctval, val, swreg, offset, code...) \
la a0, test_ ## test_num ## _data; \
li reg, val; \
code; \
fsw destreg, offset(swreg); \
lw a1, 0(a0); \
RVTEST_IO_ASSERT_SFPR_EQ(destreg, a1, correctval) \
.pushsection .data; \
.balign 2; \
test_ ## test_num ## _data: \
.word correctval; \
.popsection
// Base functions for double precision floating point operations - rv32d
#define TEST_CASE_FPD(test_num, destreg, reg1, reg2, correctval, val1, val2, swreg, offset, code... ) \
la a0, test_ ## test_num ## _data; \
fld reg1, 0(a0); \
fld reg2, 8(a0); \
code; \
fsd destreg, offset(swreg); \
lw t1, 16(a0); \
lw t2, 20(a0); \
la a0, store_ ## test_num ## _data; \
fsd destreg, 0(a0); \
lw a1, 0(a0); \
lw a2, 4(a0); \
RVTEST_IO_ASSERT_DFPR_EQ(destreg, t2, t1, a2, a1, correctval) \
.pushsection .data; \
.balign 8; \
test_ ## test_num ## _data: \
.double val1; \
.double val2; \
.dword correctval; \
.popsection; \
.pushsection .data; \
store_ ## test_num ## _data: \
.fill 1, 8, -1; \
.popsection
#define TEST_CASE_FPD_I(test_num, destreg, reg, correctval, val, swreg, offset, code... ) \
la a0, test_ ## test_num ## _data; \
code; \
fsd destreg, offset(swreg); \
lw t1, 0(a0); \
lw t2, 4(a0); \
la a0, store_ ## test_num ## _data; \
fsd destreg, 0(a0); \
lw a1, 0(a0); \
lw a2, 4(a0); \
RVTEST_IO_ASSERT_DFPR_EQ(destreg, t2, t1, a2, a1, correctval) \
.pushsection .data; \
.balign 2; \
test_ ## test_num ## _data: \
.dword correctval; \
.popsection; \
store_ ## test_num ## _data: \
.fill 1, 8, -1; \
.popsection
#define TEST_CASE_FPD_I2(test_num, destreg, reg, correctval, val, swreg, offset, code... ) \
la a0, test_ ## test_num ## _data; \
fld reg, 0(a0); \
lw t1, 8(a0); \
code; \
sw destreg, offset(swreg); \
RVTEST_IO_ASSERT_GPR_EQ(x31, destreg, correctval) \
.pushsection .data; \
.balign 4; \
test_ ## test_num ## _data: \
.double val; \
.word correctval; \
.popsection
#define TEST_CASE_FPD_4REG(test_num, destreg, reg1, reg2, reg3, correctval, val1, val2, val3, swreg, offset, code... ) \
la a0, test_ ## test_num ## _data; \
fld reg1, 0(a0); \
fld reg2, 8(a0); \
fld reg3, 16(a0); \
code; \
fsd destreg, offset(swreg); \
lw t1, 24(a0); \
lw t2, 28(a0); \
la a0, store_ ## test_num ## _data; \
fsd destreg, 0(a0); \
lw a1, 0(a0); \
lw a2, 4(a0); \
RVTEST_IO_ASSERT_DFPR_EQ(destreg, t2, t1, a2, a1, correctval) \
.pushsection .data; \
.balign 16; \
test_ ## test_num ## _data: \
.double val1; \
.double val2; \
.double val3; \
.dword correctval; \
.popsection; \
.pushsection .data; \
store_ ## test_num ## _data: \
.fill 1, 8, -1; \
.popsection
//Tests for a instructions with register-register operand
#define TEST_RR_OP(inst, destreg, reg1, reg2, correctval, val1, val2, swreg, offset) \
TEST_CASE( destreg, correctval, swreg, offset, \
li reg1, MASK_XLEN(val1); \
li reg2, MASK_XLEN(val2); \
inst destreg, reg1, reg2; \
)
#define TEST_RR_SRC1( inst, destreg, reg, correctval, val1, val2, swreg, offset) \
TEST_CASE( destreg, correctval, swreg, offset, \
li destreg, MASK_XLEN(val1); \
li reg, MASK_XLEN(val2); \
inst destreg, destreg, reg; \
)
#define TEST_RR_SRC2( inst, destreg, reg, correctval, val1, val2, swreg, offset) \
TEST_CASE( destreg, correctval, swreg, offset, \
li reg, MASK_XLEN(val1); \
li destreg, MASK_XLEN(val2); \
inst destreg, reg, destreg; \
)
#define TEST_RR_SRC12( inst, destreg, correctval, val, swreg, offset) \
TEST_CASE( destreg, correctval, swreg, offset, \
li destreg, MASK_XLEN(val1); \
inst destreg, destreg, destreg; \
)
#define TEST_RR_ZERO1( inst, destreg, reg, correctval, val, swreg, offset) \
TEST_CASE( destreg, correctval, swreg, offset, \
li reg, MASK_XLEN(val); \
inst destreg, x0, reg; \
)
#define TEST_RR_ZERO2( inst, destreg, reg, correctval, val, swreg, offset) \
TEST_CASE( destreg, correctval, swreg, offset, \
li reg, MASK_XLEN(val); \
inst destreg, reg, x0; \
)
#define TEST_RR_ZERO12( inst, destreg, correctval, swreg, offset) \
TEST_CASE( destreg, correctval, swreg, offset, \
inst destreg, x0, x0; \
)
#define TEST_RR_ZERODEST( inst, reg1, reg2, val1, val2, swreg, offset) \
TEST_CASE( x0, 0, swreg, offset, \
li reg1, MASK_XLEN(val1); \
li reg2, MASK_XLEN(val2); \
inst x0, reg1, reg2; \
)
//Tests for a instructions with register-immediate operand
#define TEST_IMM_OP( inst, destreg, reg, correctval, val, imm, swreg, offset) \
TEST_CASE ( destreg, correctval, swreg, offset, \
li reg, MASK_XLEN(val); \
inst destreg, reg, SEXT_IMM(imm); \
)
#define TEST_IMM_SRC( inst, destreg, correctval, val, imm, swreg, offset) \
TEST_CASE ( destreg, correctval, swreg, offset, \
li destreg, MASK_XLEN(val); \
inst destreg, destreg, SEXT_IMM(imm); \
)
#define TEST_IMM_ZEROSRC( inst, destreg, correctval, imm, swreg, offset) \
TEST_CASE ( destreg, correctval, swreg, offset, \
inst destreg, x0, SEXT_IMM(imm); \
)
#define TEST_IMM_ZERODEST( inst, reg, val, imm, swreg, offset) \
TEST_CASE ( x0, 0, swreg, offset, \
li reg, MASK_XLEN(val); \
inst x0, reg, SEXT_IMM(imm); \
)
#define TEST_IMM_ONEREG( inst, destreg, correctval, imm, swreg, offset) \
TEST_CASE ( destreg, correctval, swreg, offset, \
inst destreg, SEXT_IMM(imm); \
)
#define TEST_AUIPC(inst, destreg, correctval, imm, swreg, offset) \
TEST_CASE ( destreg, correctval, swreg, offset, \
1: \
inst destreg, SEXT_IMM(imm); \
la swreg, 1b; \
sub destreg, destreg, swreg; \
)
//Tests for a compressed instruction
#define TEST_CR_OP( inst, destreg, reg, correctval, val1, val2, swreg, offset) \
TEST_CASE ( destreg, correctval, swreg, offset, \
li reg, MASK_XLEN(val1); \
li destreg, MASK_XLEN(val2); \
inst destreg, reg; \
)
#define TEST_CI_OP( inst, destreg, correctval, val, imm, swreg, offset) \
TEST_CASE( destreg, correctval, swreg, offset, \
li destreg, MASK_XLEN(val); \
inst destreg, imm; \
)
#define TEST_CI_OP_NOREG(inst, correctval, imm, swreg, offset) \
TEST_CASE (x0, correctval, swreg, offset, \
inst imm; \
)
//Tests for floating point instructions - single precision
#define TEST_FP_OP(test_num, inst, destreg, reg1, reg2, correctval, val1, val2, swreg, offset) \
TEST_CASE_FP(test_num, destreg, reg1, reg2, correctval, val1, val2, swreg, offset, \
inst destreg, reg1, reg2; \
)
#define TEST_FP_ONEREG(test_num, inst, destreg, reg, correctval, val, swreg, offset) \
TEST_CASE_FP(test_num, destreg, reg, reg, correctval, val, val, swreg, offset, \
inst destreg, reg; \
)
#define TEST_FP_4REG(test_num, inst, destreg, reg1, reg2, reg3, correctval, val1, val2, val3, swreg, offset) \
TEST_CASE_FP_4REG(test_num, destreg, reg1, reg2, reg3, correctval, val1, val2, val3, swreg, offset, \
inst destreg, reg1, reg2, reg3; \
)
#define TEST_FP_I(test_num, inst, destreg, reg, correctval, val, swreg, offset) \
TEST_CASE_FP_I(test_num, destreg, reg, correctval, val, swreg, offset, \
li reg, MASK_XLEN(val); \
inst destreg, reg; \
)
#define TEST_FP_I2(test_num, inst, destreg, reg, correctval, val, swreg, offset) \
TEST_CASE_FP_I2(test_num, destreg, reg, correctval, val, swreg, offset, \
inst destreg, reg; \
)
//Tests for floating point instructions - double precision
#define TEST_FPD_OP(test_num, inst, destreg, reg1, reg2, correctval, val1, val2, swreg, offset) \
TEST_CASE_FPD(test_num, destreg, reg1, reg2, correctval, val1, val2, swreg, offset, \
inst destreg, reg1, reg2; \
)
#define TEST_FPD_ONEREG(test_num, inst, destreg, reg, correctval, val, swreg, offset) \
TEST_CASE_FPD(test_num, destreg, reg, reg, correctval, val, val, swreg, offset, \
inst destreg, reg; \
)
#define TEST_FPD_4REG(test_num, inst, destreg, reg1, reg2, reg3, correctval, val1, val2, val3, swreg, offset) \
TEST_CASE_FPD_4REG(test_num, destreg, reg1, reg2, reg3, correctval, val1, val2, val3, swreg, offset, \
inst destreg, reg1, reg2, reg3; \
)
#define TEST_FPD_I(test_num, inst, destreg, reg, correctval, val, swreg, offset) \
TEST_CASE_FPD_I(test_num, destreg, reg, correctval, val, swreg, offset, \
li reg, MASK_XLEN(val); \
inst destreg, reg; \
)
#define TEST_FPD_I2(test_num, inst, destreg, reg, correctval, val, swreg, offset) \
TEST_CASE_FPD_I2(test_num, destreg, reg, correctval, val, swreg, offset, \
inst destreg, reg; \
)
#define TEST_CADDI16SP(correctval, imm, swreg, offset) \
TEST_CASE(x2, correctval, swreg, offset, \
c.addi16sp x2, imm; \
)
#define TEST_CADDI4SPN(destreg, correctval, imm, swreg, offset) \
TEST_CASE(destreg, correctval, swreg, offset, \
c.addi4spn destreg, x2, SEXT_IMM(imm); \
)
#define TEST_CJL(inst, reg, val, swreg, offset) \
li x10, val; \
la reg, 1f; \
inst reg; \
li x10, 0x123ab; \
1: \
sw x10, offset(swreg); \
RVTEST_IO_ASSERT_GPR_EQ(x31, x10, val); \
#define ABS(x) ((x >> 11) ^ x) - (x >> 11)
#define TEST_CJ(inst, reg, val, swreg, offset) \
li reg, val; \
inst 1f; \
li reg, 0x123ab; \
1: \
sw reg, offset(swreg); \
RVTEST_IO_ASSERT_GPR_EQ(x31, reg, val); \
#define TEST_CL(inst, reg, imm, swreg, offset) \
la reg, test_data; \
inst reg, imm(reg); \
sw reg, offset(swreg); \
// lw reg, imm(x2)
// c.lwsp reg, imm(x2)
#define TEST_CLWSP(reg, imm, swreg, offset) \
la x2, test_data; \
c.lwsp reg, imm(x2); \
sw reg, offset(swreg); \
#define TEST_CSW(test_data, inst, reg1, reg2, val, imm, swreg, offset) \
li reg1, val; \
la reg2, test_data; \
inst reg1, imm(reg2); \
lw reg1, imm(reg2); \
sw reg1, offset(swreg); \
RVTEST_IO_ASSERT_GPR_EQ(x31, reg1, val); \
#define TEST_CSWSP(test_data, reg, val, imm, swreg, offset) \
la x2, test_data; \
li reg, val; \
c.swsp reg, imm(x2); \
lw reg, imm(x2); \
sw reg, offset(swreg); \
RVTEST_IO_ASSERT_GPR_EQ(x31, reg, val); \
#define TEST_CBEQZ(reg, val, swreg, offset) \
li reg, val; \
c.sub reg, reg; \
c.beqz reg, 3f; \
li reg, 0x123ab; \
3: \
sw reg, offset(swreg); \
RVTEST_IO_ASSERT_GPR_EQ(x31, reg, 0x0); \
#define TEST_CBNEZ(reg, val, swreg, offset) \
li reg, val; \
c.bnez reg, 4f; \
li reg, 0x0; \
4: \
sw reg, offset(swreg); \
RVTEST_IO_ASSERT_GPR_EQ(x31, reg, val); \
#define TEST_FMVXS(test_num, destreg, reg, correctval, val, swreg, offset) \
TEST_CASE_FP_FMVXS(test_num, destreg, reg, correctval, val, swreg, offset, \
fmv.x.s destreg, reg; \
)
#define TEST_FMVSX(test_num, destreg, reg, correctval, val, swreg, offset) \
TEST_CASE_FP_FMVSX(test_num, destreg, reg, correctval, val, swreg, offset, \
fmv.s.x destreg, reg; \
)
#define SWSIG(a,b)
#if __riscv_xlen == 64
#define SATP_MODE SATP64_MODE
#else
#define SATP_MODE SATP32_MODE
#endif
#define SATP32_MODE 0x80000000
#define SATP32_ASID 0x7FC00000
#define SATP32_PPN 0x003FFFFF
#define SATP64_MODE 0xF000000000000000
#define SATP64_ASID 0x0FFFF00000000000
#define SATP64_PPN 0x00000FFFFFFFFFFF
#define SATP_MODE_OFF 0
#define SATP_MODE_SV32 1
#define SATP_MODE_SV39 8
#define SATP_MODE_SV48 9
#define SATP_MODE_SV57 10
#define SATP_MODE_SV64 11
#define TEST_FP_OP2_D32( testnum, inst, flags, result, val1, val2 ) \
TEST_FP_OP_D32_INTERNAL( testnum, flags, double result, val1, val2, 0.0, \
inst f3, f0, f1; fsd f3, 0(a0); lw t2, 4(a0); lw a0, 0(a0))
#define TEST_CASE_D32( testnum, testreg1, testreg2, correctval, code... ) \
test_ ## testnum: \
code; \
la x31, test_ ## testnum ## _data ; \
lw x29, 0(x31); \
lw x31, 4(x31); \
li TESTNUM, testnum; \
bne testreg1, x29, fail;\
bne testreg2, x31, fail;\
.pushsection .data; \
.balign 8; \
test_ ## testnum ## _data: \
.dword correctval; \
.popsection
#define TEST_FP_OP_D32_INTERNAL( testnum, flags, result, val1, val2, val3, code... ) \
test_ ## testnum: \
li TESTNUM, testnum; \
la a0, test_ ## testnum ## _data ;\
fld f0, 0(a0); \
fld f1, 8(a0); \
fld f2, 16(a0); \
lw a3, 24(a0); \
lw t1, 28(a0); \
code; \
fsflags a1, x0; \
li a2, flags; \
bne a0, a3, fail; \
bne t1, t2, fail; \
bne a1, a2, fail; \
.pushsection .data; \
.balign 8; \
test_ ## testnum ## _data: \
.double val1; \
.double val2; \
.double val3; \
.result; \
.popsection
#define TEST_FP_OP1_D32( testnum, inst, flags, result, val1 ) \
TEST_FP_OP_D32_INTERNAL( testnum, flags, double result, val1, 0.0, 0.0, \
inst f3, f0; fsd f3, 0(a0); lw t2, 4(a0); lw a0, 0(a0))
#define TEST_FCLASS_D32(testnum, correct, input) \
TEST_CASE(testnum, a0, correct, \
la a0, test_ ## testnum ## _data ;\
fld fa0, 0(a0); \
fclass.d a0, fa0) \
.pushsection .data; \
.balign 8; \
test_ ## testnum ## _data: \
.dword input; \
.popsection
#define TEST_FP_CMP_OP_D32( testnum, inst, flags, result, val1, val2 ) \
TEST_FP_OP_D32_INTERNAL( testnum, flags, dword result, val1, val2, 0.0, \
inst a0, f0, f1; li t2, 0)
#define TEST_INT_FP_OP_D32( testnum, inst, result, val1 ) \
test_ ## testnum: \
li TESTNUM, testnum; \
la a0, test_ ## testnum ## _data ;\
lw a3, 0(a0); \
lw a4, 4(a0); \
li a1, val1; \
inst f0, a1; \
\
fsd f0, 0(a0); \
lw a1, 4(a0); \
lw a0, 0(a0); \
\
fsflags x0; \
bne a0, a3, fail; \
bne a1, a4, fail; \
.pushsection .data; \
.balign 8; \
test_ ## testnum ## _data: \
.double result; \
.popsection
#define TEST_FCVT_S_D32( testnum, result, val1 ) \
TEST_FP_OP_D32_INTERNAL( testnum, 0, double result, val1, 0.0, 0.0, \
fcvt.s.d f3, f0; fcvt.d.s f3, f3; fsd f3, 0(a0); lw t2, 4(a0); lw a0, 0(a0))
#define TEST_FP_OP3_D32( testnum, inst, flags, result, val1, val2, val3 ) \
TEST_FP_OP_D32_INTERNAL( testnum, flags, double result, val1, val2, val3, \
inst f3, f0, f1, f2; fsd f3, 0(a0); lw t2, 4(a0); lw a0, 0(a0))
#define TEST_FP_OP1_D32_DWORD_RESULT( testnum, inst, flags, result, val1 ) \
TEST_FP_OP_D32_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \
inst f3, f0; fsd f3, 0(a0); lw t2, 4(a0); lw a0, 0(a0))
#endif