Init
This commit is contained in:
Mikhail Yenuchenko
260
sim/tests/riscv_arch/Makefile
Normal file
260
sim/tests/riscv_arch/Makefile
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@@ -0,0 +1,260 @@
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## @file
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## Syntacore SCR* tests
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##
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## @copyright 2015-2018 Syntacore. All rights reserved.
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## RISCV-Compliance
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##
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XLEN ?= 32
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ABI ?= ilp32
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ARCH ?=im
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override ARCH :=rv$(XLEN)$(ARCH)
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$(info >>> ARCH := $(ARCH))
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src_dir := $(CURDIR)
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RISCV_ARCH_TESTS := $(src_dir)/../../../dependencies/riscv-arch/
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#I IM IMC IC
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#EM EMC EC
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ifeq (e,$(findstring e, $(ARCH)))
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ifeq (e,$(findstring e,$(ARCH)))
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$(info >>> E32 TESTS)
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included_e += $(filter %.S,\
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$(wildcard $(RISCV_ARCH_TESTS)/riscv-test-suite/rv32e_unratified/E/src/*))
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arch_set += $(included_e)
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reference_src += $(wildcard $(RISCV_ARCH_TESTS)/riscv-test-suite/rv32e_unratified/E/*/*.reference_output)
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endif
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ifeq (c,$(findstring c,$(ARCH)))
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$(info >>> EC32 TESTS)
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included_ec += $(filter %.S,\
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$(wildcard $(RISCV_ARCH_TESTS)/riscv-test-suite/rv32e_unratified/C/src/*))
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arch_set += $(included_ec)
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reference_src += $(wildcard $(RISCV_ARCH_TESTS)/riscv-test-suite/rv32e_unratified/C/*/*.reference_output)
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endif
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ifeq (m,$(findstring m,$(ARCH)))
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$(info >>> EM32 TESTS)
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included_em += $(filter %.S,\
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$(wildcard $(RISCV_ARCH_TESTS)/riscv-test-suite/rv32e_unratified/M/src/*))
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arch_set += $(included_em)
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reference_src += $(wildcard $(RISCV_ARCH_TESTS)/riscv-test-suite/rv32e_unratified/M/*/*.reference_output)
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endif
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else ## ifdef SCR_BASE_RVE_EXT
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ifeq (i,$(findstring i, $(ARCH)))
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ifeq (i,$(findstring i,$(ARCH)))
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$(info >>> I32 TESTS)
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included_i += $(filter %.S,\
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$(wildcard $(RISCV_ARCH_TESTS)/riscv-test-suite/rv32i_m/I/src/*))
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included_ip += $(filter %.S,\
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$(wildcard $(RISCV_ARCH_TESTS)/riscv-test-suite/rv32i_m/privilege/src/*))
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included_i += $(filter %.S,\
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$(wildcard $(RISCV_ARCH_TESTS)/riscv-test-suite/rv32i_m/Zifencei/src/*))
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included_i += $(included_ip)
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arch_set += $(included_i)
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reference_src += $(wildcard $(RISCV_ARCH_TESTS)/riscv-test-suite/rv32i_m/I/*/*.reference_output)
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reference_src += $(wildcard $(RISCV_ARCH_TESTS)/riscv-test-suite/rv32i_m/privilege/*/*.reference_output)
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reference_src += $(wildcard $(RISCV_ARCH_TESTS)/riscv-test-suite/rv32i_m/Zifencei/*/*.reference_output)
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endif
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ifeq (c,$(findstring c,$(ARCH)))
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$(info >>> IC32 TESTS)
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included_ic += $(filter %.S,\
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$(wildcard $(RISCV_ARCH_TESTS)/riscv-test-suite/rv32i_m/C/src/*))
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arch_set += $(included_ic)
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reference_src += $(wildcard $(RISCV_ARCH_TESTS)/riscv-test-suite/rv32i_m/C/*/*.reference_output)
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endif
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ifeq (m,$(findstring m,$(ARCH)))
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$(info >>> IM32 TESTS)
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included_im += $(filter %.S,\
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$(wildcard $(RISCV_ARCH_TESTS)/riscv-test-suite/rv32i_m/M/src/*))
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arch_set += $(included_im)
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reference_src += $(wildcard $(RISCV_ARCH_TESTS)/riscv-test-suite/rv32i_m/M/*/*.reference_output)
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endif
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endif
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endif
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$(info >>>$(ARCH) set included)
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ifeq ($(arch_set),)
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$(info >>> No arch tests included)
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endif
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$(info >>>>> arch set: $(arch_set))
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dst_dir := $(bld_dir)
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test_name := riscv_arch
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bld_dir := $(addprefix $(dst_dir)/, $(test_name))
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obj_dir := $(bld_dir)/riscv_arch_objs
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ifeq ($(ARCH),$(filter $(ARCH),rv32im))
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cut_list += misalign-blt-01 misalign-jal-01 misalign-beq-01 misalign2-jalr-01 misalign-bgeu-01 misalign-bltu-01 misalign-bge-01 misalign-bne-01 # privilege test used mtvec
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endif
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ifeq ($(ARCH),$(filter $(ARCH),rv32ic))
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cut_list += misalign-lw-01 misalign-sh-01 misalign-lhu-01 misalign-lh-01 ecall misalign-sw-01 # privilege test used mtvec
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endif
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cut_list += bne-01 blt-01 beq-01 bge-01 jal-01 bltu-01 bgeu-01 # i - base
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cut_list += ebreak cebreak-01 cswsp-01 # C - base
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testnames := $(basename $(notdir $(arch_set)))
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filtered := $(filter-out $(cut_list),$(testnames))
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objs := $(addprefix $(bld_dir)/,$(filtered:%=%.o))
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test_elf := $(addprefix $(dst_dir)/arch_,$(filtered:%=%.elf))
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test_hex := $(addprefix $(dst_dir)/arch_,$(filtered:%=%.hex))
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test_dump := $(addprefix $(bld_dir)/arch_,$(filtered:%=%.dump))
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arch_macros_file := $(root_dir)/sim/tests/riscv_arch/model_test.h
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arch_output ?= true
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ifeq (e,$(findstring e,$(ARCH)))
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EXT_CFLAGS += -DRVTEST_E
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endif
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# Set name file for RV32I
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testnames_i := $(basename $(notdir $(included_i)))
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testnames_im := $(basename $(notdir $(included_im)))
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testnames_ic := $(basename $(notdir $(included_ic)))
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testnames_ib := $(basename $(notdir $(included_ib)))
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filtered_i := $(filter-out $(cut_list),$(testnames_i))
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filtered_im := $(filter-out $(cut_list),$(testnames_im))
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filtered_ic := $(filter-out $(cut_list),$(testnames_ic))
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filtered_ib := $(filter-out $(cut_list),$(testnames_ib))
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# Set name file for RVE
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testnames_e := $(basename $(notdir $(included_e)))
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testnames_em := $(basename $(notdir $(included_em)))
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testnames_ec := $(basename $(notdir $(included_ec)))
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filtered_e := $(filter-out $(cut_list),$(testnames_e))
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filtered_em := $(filter-out $(cut_list),$(testnames_em))
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filtered_ec := $(filter-out $(cut_list),$(testnames_ec))
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CFLAGS := -I$(inc_dir) -I$(src_dir) -DASM -mabi=$(ABI) $(EXT_CFLAGS) -DXLEN=$(XLEN) -D__riscv_xlen=$(XLEN) -w
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LDFLAGS := -static -fvisibility=hidden -nostdlib -nostartfiles -T$(inc_dir)/link.ld -march=$(ARCH) -mabi=$(ABI)
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GCCVERSIONGT7 := $(shell expr `$(RISCV_GCC) -dumpfullversion | cut -f1 -d'.'` \> 7)
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ifeq "$(GCCVERSIONGT7)" "1"
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LDFLAGS += -mno-relax
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endif
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VPATH += $(src_dir) $(bld_dir) $(obj_dir) $(asm_path) $(ref_path) $(RISCV_ARCH_TESTS)
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ifeq ($(arch_output), true)
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CFLAGS += -D_ARCH_OUTPUT
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endif
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default: clean log_requested_tgt check_version cp_asm ref_data $(test_elf) $(test_hex) $(test_dump)
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define compile_template
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$(obj_dir)/$(1).o: $(obj_dir) cp_asm
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$(RISCV_GCC) -c $$(bld_dir)/arch_asm/$(1).S $$(CFLAGS) -Wa,$(2) $(2) -o $$@
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endef
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define preprocessing
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for test_asm in $(1); do \
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march_tmp=$$test_asm ; \
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march_tmp=$${march_tmp%/src*} ; \
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march_tmp=$$(basename $$march_tmp) ; \
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file_name="$$(basename $${test_asm})" ; \
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$(RISCV_GCC) $(CFLAGS) -Wa,$(2) $(2) -E $$test_asm \
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-o $(bld_dir)/arch_asm/$$file_name ; \
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done
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endef
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define preprocessing_privilege
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for test_asm in $(1); do \
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march_tmp=$$test_asm ; \
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march_tmp=$${march_tmp%/src*} ; \
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march_tmp=$$(basename $$march_tmp) ; \
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file_name="$$(basename $${test_asm})" ; \
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$(RISCV_GCC) $(CFLAGS) -Drvtest_mtrap_routine=True -Dmhandler -Wa,$(2) $(2) -E $$test_asm \
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-o $(bld_dir)/arch_asm/$$file_name ; \
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done
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endef
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$(foreach SRC,$(filtered_i),$(eval $(call compile_template,$(SRC),-march=rv32i_zicsr_zifencei)))
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$(foreach SRC,$(filtered_im),$(eval $(call compile_template,$(SRC),-march=rv32im_zicsr_zifencei)))
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$(foreach SRC,$(filtered_ic),$(eval $(call compile_template,$(SRC),-march=rv32ic_zicsr_zifencei)))
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$(foreach SRC,$(filtered_e),$(eval $(call compile_template,$(SRC),-march=rv32e_zicsr_zifencei)))
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$(foreach SRC,$(filtered_em),$(eval $(call compile_template,$(SRC),-march=rv32em_zicsr_zifencei)))
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$(foreach SRC,$(filtered_ec),$(eval $(call compile_template,$(SRC),-march=rv32ec_zicsr_zifencei)))
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log_requested_tgt: $(bld_dir)
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$(foreach test_name, $(filtered), $(eval $(shell echo arch_$(test_name).hex >> $(bld_dir)/../test_info)))
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$(bld_dir) :
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mkdir -p $(bld_dir)
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$(obj_dir) : | ref_data
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mkdir -p $(obj_dir)
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$(dst_dir)/arch_%.elf: $(obj_dir)/%.o | $(dep_files)
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$(RISCV_GCC) $^ $(LDFLAGS) -o $@ -g
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$(dst_dir)/arch_%.hex: $(dst_dir)/arch_%.elf
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$(RISCV_OBJCOPY) $^ $@
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$(bld_dir)/arch_%.dump: $(dst_dir)/arch_%.elf
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$(RISCV_OBJDUMP) -D -w -x -S $^ > $@
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ref_data:
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mkdir -p $(bld_dir)/ref_data
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for files in $(reference_src) ; do \
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sed_input=$$files ; \
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sed_output=$$(basename $${files%.*}) ; \
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sed "s/\r$$//; \
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s/\(........\)/\1,/g; \
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s/.$$//; s/\(.*\),\(.*\),\(.*\),\(.*\)/\4,\3,\2,\1/;" \
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$$sed_input > $(bld_dir)/ref_data/$$sed_output; \
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done
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cp_asm:
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mkdir -p $(bld_dir)/arch_asm
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$(call preprocessing,$(included_i),-march=rv32i)
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$(call preprocessing_privilege,$(included_ip),-march=rv32i)
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$(call preprocessing,$(included_im),-march=rv32im)
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$(call preprocessing,$(included_ic),-march=rv32ic)
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$(call preprocessing,$(included_e),-march=rv32e)
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$(call preprocessing,$(included_em),-march=rv32em)
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$(call preprocessing,$(included_ec),-march=rv32ec)
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riscv_arch_tests_dir := $(if $(RISCV_ARCH_TESTS), $(RISCV_ARCH_TESTS), ./undefined)
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riscv_tests_commit := 9141cf9274b610d059199e8aa2e21f54a0bc6a6e
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## commit hash readed from local copy of https://github.com/riscv/riscv-arch-test.git
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tmp_commit = $(shell cd $(riscv_arch_tests_dir) 2>/dev/null && git log -1 | grep "commit" | cut -f2 -d ' ')
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is_commit_good = $(if $(subst $(riscv_tests_commit),,$(tmp_commit)),false,true)
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# Color
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RED=\033[0;31m
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NC=\033[0m
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check_version : $(riscv_arch_tests_dir)
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@if [ ! -d $(riscv_arch_tests_dir) ]; then \
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echo -e "$(RED)==========================================================================" &&\
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echo " Error! Environment variable RISCV_ARCH_TESTS='$(riscv_arch_tests_dir)' " &&\
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echo " directory not exist!" && \
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echo "==========================================================================$(NC)" ; \
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fi
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ifneq ($(is_commit_good),true)
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@echo -e "$(RED)=========================================================================="
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@echo " Warning! Execution of test code is not guaranteed "
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@echo " while using the current commit of repository located at : $(riscv_arch_tests_dir) ."
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@echo " "
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@echo " riscv_arch repository must point to commit $(riscv_tests_commit)!"
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@echo -e "==========================================================================$(NC)"
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endif
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$(riscv_arch_tests_dir) :.
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ifndef RISCV_ARCH_TESTS
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@echo -e "$(RED)=========================================================================="
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@echo " Error! Environment variable RISCV_ARCH_TESTS not set!"
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@echo " You must set the environment variable RISCV_ARCH_TESTS"
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@echo " The variable should point to the local copy of the"
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@echo " repository https://github.com/riscv/riscv-arch-test.git"
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@echo " with the commit $(riscv_tests_commit)"
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@echo -e "==========================================================================$(NC)"
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exit 1
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endif
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clean:
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$(RM) -R $(test_elf) $(test_hex) $(bld_dir)
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.PHONY: check_version clean ref_data cp_asm default
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1041
sim/tests/riscv_arch/arch_test.h
Normal file
1041
sim/tests/riscv_arch/arch_test.h
Normal file
File diff suppressed because it is too large
Load Diff
1495
sim/tests/riscv_arch/encoding.h
Normal file
1495
sim/tests/riscv_arch/encoding.h
Normal file
File diff suppressed because it is too large
Load Diff
103
sim/tests/riscv_arch/model_test.h
Normal file
103
sim/tests/riscv_arch/model_test.h
Normal file
@@ -0,0 +1,103 @@
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// RISC-V Compliance Test Header File
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// Copyright (c) 2017, Codasip Ltd. All Rights Reserved.
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// See LICENSE for license details.
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//
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// Description: Common header file for RV32I tests
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#ifndef _COMPLIANCE_TEST_H
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#define _COMPLIANCE_TEST_H
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#include "riscv_test.h"
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#include "encoding.h"
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//-----------------------------------------------------------------------
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// RV Compliance Macros
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//-----------------------------------------------------------------------
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#define RV_COMPLIANCE_HALT \
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#define RV_COMPLIANCE_RV32M \
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RVTEST_RV32M \
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#define RV_COMPLIANCE_CODE_BEGIN \
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RVTEST_CODE_BEGIN_OLD \
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#define RV_COMPLIANCE_CODE_END \
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RVTEST_CODE_END_OLD \
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#define RV_COMPLIANCE_DATA_BEGIN \
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RVTEST_DATA_BEGIN_OLD \
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#define RV_COMPLIANCE_DATA_END \
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RVTEST_DATA_END_OLD \
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#endif// RISC-V Compliance IO Test Header File
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/*
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* Copyright (c) 2005-2018 Imperas Software Ltd., www.imperas.com
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*
|
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* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
* either express or implied.
|
||||
*
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
*/
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||||
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#ifndef _COMPLIANCE_IO_H
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#define _COMPLIANCE_IO_H
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//-----------------------------------------------------------------------
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// RV IO Macros (Non functional)
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//-----------------------------------------------------------------------
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#ifdef _ARCH_OUTPUT
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#define RVTEST_IO_PUSH(_SP) \
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la _SP, begin_regstate; \
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sw x3, 0(_SP); \
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sw x4, 4(_SP); \
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sw x5, 8(_SP);
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#define RVTEST_IO_POP(_SP) \
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la _SP, begin_regstate; \
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lw x3, 0(_SP); \
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lw x4, 4(_SP); \
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lw x5, 8(_SP);
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#define RVTEST_IO_WRITE_STR(_SP, _STR) \
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.section .data.string; \
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20001: \
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.string _STR; \
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.section .text.init; \
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RVTEST_IO_PUSH(_SP) \
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li x3, 0xF0000000; \
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la x4, 20001b; \
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2: lb x5, 0(x4); \
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sb x5, 0(x3); \
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beq x5, zero, 1f; \
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add x4, x4, 1; \
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j 2b; \
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1: RVTEST_IO_POP(_SP)
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#else // #ifdef _ARCH_OUTPUT
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#define RVTEST_IO_WRITE_STR(_SP, _STR)
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#endif // #end #ifdef _ARCH_OUTPUT
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#define RVTEST_IO_INIT
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#define RVTEST_IO_CHECK()
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#define RVTEST_IO_ASSERT_GPR_EQ(_SP, _R, _I)
|
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#define RVTEST_IO_ASSERT_SFPR_EQ(_F, _R, _I)
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#define RVTEST_IO_ASSERT_DFPR_EQ(_D, _R, _I)
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#define RVTEST_IO_ASSERT_EQ(_R, _I)
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#endif // _COMPLIANCE_IO_H
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253
sim/tests/riscv_arch/riscv_test.h
Normal file
253
sim/tests/riscv_arch/riscv_test.h
Normal file
@@ -0,0 +1,253 @@
|
||||
// See LICENSE for license details.
|
||||
|
||||
#ifndef _ENV_PHYSICAL_SINGLE_CORE_H
|
||||
#define _ENV_PHYSICAL_SINGLE_CORE_H
|
||||
|
||||
#include "encoding.h"
|
||||
#include "sc_test.h"
|
||||
.noaltmacro
|
||||
|
||||
//-----------------------------------------------------------------------
|
||||
// Begin Macro
|
||||
//-----------------------------------------------------------------------
|
||||
|
||||
#define RVTEST_RV64U \
|
||||
.macro init; \
|
||||
.endm
|
||||
|
||||
#define RVTEST_RV64UF \
|
||||
.macro init; \
|
||||
RVTEST_FP_ENABLE; \
|
||||
.endm
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||||
|
||||
#define RVTEST_RV32U \
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||||
.macro init; \
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||||
.endm
|
||||
|
||||
#define RVTEST_RV32UF \
|
||||
.macro init; \
|
||||
RVTEST_FP_ENABLE; \
|
||||
.endm
|
||||
|
||||
#define RVTEST_RV64M \
|
||||
.macro init; \
|
||||
RVTEST_ENABLE_MACHINE; \
|
||||
.endm
|
||||
|
||||
#define RVTEST_RV64S \
|
||||
.macro init; \
|
||||
RVTEST_ENABLE_SUPERVISOR; \
|
||||
.endm
|
||||
|
||||
#define RVTEST_RV32M \
|
||||
.macro init; \
|
||||
RVTEST_ENABLE_MACHINE; \
|
||||
.endm
|
||||
|
||||
#define RVTEST_RV32S \
|
||||
.macro init; \
|
||||
RVTEST_ENABLE_SUPERVISOR; \
|
||||
.endm
|
||||
|
||||
#if __riscv_xlen == 64
|
||||
# define CHECK_XLEN li a0, 1; slli a0, a0, 31; bgez a0, 1f; RVTEST_PASS; 1:
|
||||
#else
|
||||
# define CHECK_XLEN li a0, 1; slli a0, a0, 31; bltz a0, 1f; RVTEST_PASS; 1:
|
||||
#endif
|
||||
|
||||
#define INIT_PMP \
|
||||
la t0, 1f; \
|
||||
csrw mtvec, t0; \
|
||||
li t0, -1; /* Set up a PMP to permit all accesses */ \
|
||||
csrw pmpaddr0, t0; \
|
||||
li t0, PMP_NAPOT | PMP_R | PMP_W | PMP_X; \
|
||||
csrw pmpcfg0, t0; \
|
||||
.align 2; \
|
||||
1:
|
||||
|
||||
#define INIT_SATP \
|
||||
la t0, 1f; \
|
||||
csrw mtvec, t0; \
|
||||
csrwi satp, 0; \
|
||||
.align 2; \
|
||||
1:
|
||||
|
||||
#define DELEGATE_NO_TRAPS \
|
||||
la t0, 1f; \
|
||||
csrw mtvec, t0; \
|
||||
csrwi medeleg, 0; \
|
||||
csrwi mideleg, 0; \
|
||||
csrwi mie, 0; \
|
||||
.align 2; \
|
||||
1:
|
||||
|
||||
#define RVTEST_ENABLE_SUPERVISOR \
|
||||
li a0, MSTATUS_MPP & (MSTATUS_MPP >> 1); \
|
||||
csrs mstatus, a0; \
|
||||
li a0, SIP_SSIP | SIP_STIP; \
|
||||
csrs mideleg, a0; \
|
||||
|
||||
#define RVTEST_ENABLE_MACHINE \
|
||||
li a0, MSTATUS_MPP; \
|
||||
csrs mstatus, a0; \
|
||||
|
||||
#define RVTEST_FP_ENABLE \
|
||||
li a0, MSTATUS_FS & (MSTATUS_FS >> 1); \
|
||||
csrs mstatus, a0; \
|
||||
csrwi fcsr, 0
|
||||
|
||||
#define RISCV_MULTICORE_DISABLE \
|
||||
csrr a0, mhartid; \
|
||||
1: bnez a0, 1b
|
||||
|
||||
#define EXTRA_TVEC_USER
|
||||
#define EXTRA_TVEC_MACHINE
|
||||
#define EXTRA_INIT
|
||||
#define EXTRA_INIT_TIMER
|
||||
|
||||
#define PRIV_MISA_S 0
|
||||
//
|
||||
// undefine some unusable CSR Accesses if no PRIV Mode present
|
||||
//
|
||||
#if defined(PRIV_MISA_S)
|
||||
# if (PRIV_MISA_S==0)
|
||||
# undef INIT_SATP
|
||||
# define INIT_SATP
|
||||
# undef INIT_PMP
|
||||
# define INIT_PMP
|
||||
# undef DELEGATE_NO_TRAPS
|
||||
# define DELEGATE_NO_TRAPS
|
||||
# undef RVTEST_ENABLE_SUPERVISOR
|
||||
# define RVTEST_ENABLE_SUPERVISOR
|
||||
# endif
|
||||
#endif
|
||||
#if defined(PRIV_MISA_U)
|
||||
# if (PRIV_MISA_U==0)
|
||||
# endif
|
||||
#endif
|
||||
#if defined(TRAPHANDLER)
|
||||
#include TRAPHANDLER
|
||||
#endif
|
||||
|
||||
#define INTERRUPT_HANDLER j other_exception /* No interrupts should occur */
|
||||
|
||||
#define RVTEST_CODE_BEGIN_OLD \
|
||||
.section .text.init; \
|
||||
.balign 512; \
|
||||
.weak stvec_handler; \
|
||||
.weak mtvec_handler; \
|
||||
.globl _start; \
|
||||
_start: \
|
||||
/* reset vector */ \
|
||||
j reset_vector; \
|
||||
.balign 64; \
|
||||
trap_vector: \
|
||||
/* test whether the test came from pass/fail */ \
|
||||
csrr a4, mcause; \
|
||||
li a5, CAUSE_USER_ECALL; \
|
||||
beq a4, a5, write_tohost; \
|
||||
li a5, CAUSE_SUPERVISOR_ECALL; \
|
||||
beq a4, a5, write_tohost; \
|
||||
li a5, CAUSE_MACHINE_ECALL; \
|
||||
beq a4, a5, write_tohost; \
|
||||
/* if an mtvec_handler is defined, jump to it */ \
|
||||
la a4, mtvec_handler; \
|
||||
beqz a4, 1f; \
|
||||
jr a4; \
|
||||
/* was it an interrupt or an exception? */ \
|
||||
1: csrr a4, mcause; \
|
||||
bgez a4, handle_exception; \
|
||||
INTERRUPT_HANDLER; \
|
||||
handle_exception: \
|
||||
/* we don't know how to handle whatever the exception was */ \
|
||||
other_exception: \
|
||||
/* some unhandlable exception occurred */ \
|
||||
1: ori TESTNUM, TESTNUM, 1337; \
|
||||
write_tohost: \
|
||||
tail sc_exit; \
|
||||
reset_vector: \
|
||||
RISCV_MULTICORE_DISABLE; \
|
||||
INIT_SATP; \
|
||||
INIT_PMP; \
|
||||
DELEGATE_NO_TRAPS; \
|
||||
li TESTNUM, 0; \
|
||||
la t0, trap_vector; \
|
||||
csrw mtvec, t0; \
|
||||
CHECK_XLEN; \
|
||||
/* if an stvec_handler is defined, delegate exceptions to it */ \
|
||||
la t0, stvec_handler; \
|
||||
beqz t0, 1f; \
|
||||
csrw stvec, t0; \
|
||||
li t0, (1 << CAUSE_LOAD_PAGE_FAULT) | \
|
||||
(1 << CAUSE_STORE_PAGE_FAULT) | \
|
||||
(1 << CAUSE_FETCH_PAGE_FAULT) | \
|
||||
(1 << CAUSE_MISALIGNED_FETCH) | \
|
||||
(1 << CAUSE_USER_ECALL) | \
|
||||
(1 << CAUSE_BREAKPOINT); \
|
||||
csrw medeleg, t0; \
|
||||
csrr t1, medeleg; \
|
||||
bne t0, t1, other_exception; \
|
||||
1: csrwi mstatus, 0; \
|
||||
init; \
|
||||
EXTRA_INIT; \
|
||||
EXTRA_INIT_TIMER; \
|
||||
la t0, 1f; \
|
||||
csrw mepc, t0; \
|
||||
csrr a0, mhartid; \
|
||||
mret; \
|
||||
1: \
|
||||
begin_testcode:
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------
|
||||
// End Macro
|
||||
//-----------------------------------------------------------------------
|
||||
|
||||
#define RVTEST_CODE_END_OLD \
|
||||
end_testcode: \
|
||||
ecall;
|
||||
|
||||
//-----------------------------------------------------------------------
|
||||
// Pass/Fail Macro
|
||||
//-----------------------------------------------------------------------
|
||||
#define RVTEST_SYNC fence
|
||||
//#define RVTEST_SYNC nop
|
||||
|
||||
#define RVTEST_PASS \
|
||||
RVTEST_SYNC; \
|
||||
li TESTNUM, 1; \
|
||||
SWSIG (0, TESTNUM); \
|
||||
ecall
|
||||
|
||||
#define TESTNUM gp
|
||||
#define RVTEST_FAIL \
|
||||
RVTEST_SYNC; \
|
||||
1: beqz TESTNUM, 1b; \
|
||||
sll TESTNUM, TESTNUM, 1; \
|
||||
or TESTNUM, TESTNUM, 1; \
|
||||
SWSIG (0, TESTNUM); \
|
||||
la x1, end_testcode; \
|
||||
jr x1;
|
||||
|
||||
//-----------------------------------------------------------------------
|
||||
// Data Section Macro
|
||||
//-----------------------------------------------------------------------
|
||||
|
||||
#define EXTRA_DATA
|
||||
|
||||
#define RVTEST_DATA_BEGIN_OLD \
|
||||
.align 4; .global begin_signature; begin_signature:
|
||||
|
||||
#define RVTEST_DATA_END_OLD \
|
||||
.balign 4; .global end_signature; end_signature: \
|
||||
EXTRA_DATA \
|
||||
.pushsection .tohost,"aw",@progbits; \
|
||||
.align 8; .global tohost; tohost: .dword 0; \
|
||||
.align 8; .global fromhost; fromhost: .dword 0; \
|
||||
.popsection; \
|
||||
.align 8; .global begin_regstate; begin_regstate: \
|
||||
.word 128; \
|
||||
.align 8; .global end_regstate; end_regstate: \
|
||||
.word 4;
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user