Init
This commit is contained in:
Mikhail Yenuchenko
291
sim/tests/isr_sample/isr_sample.S
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291
sim/tests/isr_sample/isr_sample.S
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#include "riscv_macros.h"
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#include "sc_test.h"
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.altmacro
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// global interrupt bit
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#define MSIE (1 << IRQ_M_SOFT) //machine software interrupt enable
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#define MTIE (1 << IRQ_M_TIMER) //machine timer interrupt enable
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#define MEIE (1 << IRQ_M_EXT) //machine external interrupt enable
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#define MCAUSE_EXT_IRQ (1 << 31 | IRQ_M_EXT)
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#define MCAUSE_SOFT_IRQ (1 << 31 | IRQ_M_SOFT)
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#define MCAUSE_TMR_IRQ (1 << 31 | IRQ_M_TIMER)
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// IPIC
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#define IRQ_LINES_ADDR 0xF0000100 // simulation
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#define TRIG_EXT_IRQ_ADDR 0xF0000100 // external irq is triggered when tb memory is set to non-zero
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#define TRIG_SW_IRQ_ADDR 0xF0000200 // software irq is triggered when tb memory is set to non-zero
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#define IPIC_EOI 0xBF4 // end of interrupt
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#define IPIC_SOI 0xBF5 // start of interrupt
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#define IPIC_IDX 0xBF6 // index register
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#define IPIC_ICSR 0xBF7 // interrupt control status register
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// IPIC Interrupt Constrol Status Register
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#define IPIC_ICSR_IP (1 << 0) // interrupt pending
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#define IPIC_ICSR_IE (1 << 1) // interrupt enable
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#define IPIC_ICSR_IM (1 << 2) // interrupt mode (0/1: level/edge)
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#define IPIC_ICSR_INV (1 << 3) // line inversion
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#define IPIC_ICSR_IS (1 << 4) // in service
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// Interrupt lines in use
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#define IPIC_IRQ_LINE9 9
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#define EXT_IRQ_LINE_COMMON 0
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#include "timer.h"
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#include "reloc.h"
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.macro jmp_sc_exit
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la t0, sc_exit
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jr t0
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.endm
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.section .text.init
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.option norvc
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.globl _start
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// -----------------------------------------------------------------
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// Trap handlers
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// 0xXXXXXX00
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.option norvc
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.org (64*3)
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//0xXXXXXXC0
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.balign 64
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machine_trap_entry:
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vec_usr_soft:
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#ifdef VECT_IRQ_ENABLED
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trap_entry:
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j _trap_fail
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vec_supervisor_soft:
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j _trap_fail
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vec_reserved1:
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j _trap_fail
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vec_machine_soft:
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j vec_machine_soft_handler
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vec_usr_tmr:
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j _trap_fail
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vec_supervisor_tmr:
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j _trap_fail
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vec_reserved2:
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j _trap_fail
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vec_machine_tmr:
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j vec_machine_tmr_handler
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vec_usr_ext:
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j _trap_fail
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vec_supervisor_ext:
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j _trap_fail
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vec_reserved3:
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j _trap_fail
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vec_machine_ext:
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j vec_machine_ext_handler
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vec_reserved4:
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j _trap_fail
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j _trap_fail
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j _trap_fail
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j _trap_fail
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#else
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trap_entry:
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j direct_irq_handler
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vec_supervisor_soft:
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j _trap_fail
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vec_reserved1:
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j _trap_fail
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vec_machine_soft:
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j _trap_fail
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vec_usr_tmr:
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j _trap_fail
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vec_supervisor_tmr:
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j _trap_fail
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vec_reserved2:
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j _trap_fail
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vec_machine_tmr:
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j _trap_fail
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vec_usr_ext:
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j _trap_fail
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vec_supervisor_ext:
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j _trap_fail
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vec_reserved3:
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j _trap_fail
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vec_machine_ext:
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j _trap_fail
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vec_reserved4:
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j _trap_fail
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j _trap_fail
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j _trap_fail
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j _trap_fail
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#endif // ifdef VECT_IRQ_ENABLED
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.balign 64
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_start:
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la t0, machine_trap_entry
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csrw mtvec, t0
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la t0, test_start
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jr (t0)
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// -----------------------------------------------------------------
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.option norvc
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.balign 64
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test_start:
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la t0, trap_entry
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csrw mtvec, t0 // set mtvec to trap_entry
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#ifdef VECT_IRQ_ENABLED
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csrsi mtvec, 1 // set vectored mode
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#else
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csrsi mtvec, 0 // set direct mode
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#endif
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/// configuring timer interrupt ///
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_reset_mtimecmp; // reset timer
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_run_timer; // run timer
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csrs mstatus, MSTATUS_MIE // enable global interrupt
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li a0, MTIE
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csrs mie, a0 // enable timer interrupt
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li t2, 0 // reset timer counter = 0 (updated in isr)
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_read_mtime s1 // read timer value
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addi s1, s1, 256
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_write_mtimecmp_32 s1
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wfi
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/// configuring external interrupt ///
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csrw mie, zero // disable all interrupts
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li t0, IRQ_LINES_ADDR
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sh zero, (t0) // set all exterinal interrupt lines low
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#ifdef IPIC_ENABLED
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li t0, IPIC_IRQ_LINE9
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csrw IPIC_IDX, t0 // set IPIC to expect interupt on line 9...
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li t0, (IPIC_ICSR_IE | IPIC_ICSR_IM)
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csrw IPIC_ICSR, t0 // ....enable interrupt,set edge interrupt mode
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#endif
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li t0, MEIE
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csrs mie, t0 // enable external interrupt
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li t0, TRIG_EXT_IRQ_ADDR
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#ifdef IPIC_ENABLED
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li t1, (1 << IPIC_IRQ_LINE9)
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#else
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li t1, (1 << EXT_IRQ_LINE_COMMON)
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#endif
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sh t1, (t0) //send command to generate external interrupt on line 9 to testbench
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nop
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nop
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nop
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nop //wait for external interrupt
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/// configuring software interrupt ///
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csrw mie, zero // disable all interrupts
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li t0, TRIG_SW_IRQ_ADDR
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li t1, 0x00000001
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sh t1, (t0) //send command to generate software interrupt
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li t0, MSIE
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csrs mie, t0 // enable software interrupt
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nop
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nop
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nop
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nop //wait for software interrupt
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li s1, 3
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li a0, 0
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beq t2, s1, 1f
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li a0, -1
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1:
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jmp_sc_exit
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#ifndef VECT_IRQ_ENABLED
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direct_irq_handler:
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csrr a1, mcause
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li a5, MCAUSE_TMR_IRQ //0x80000007 -- mcause = tmr.irq
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beq a1, a5, vec_machine_tmr_handler
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li a5, MCAUSE_SOFT_IRQ //0x80000003 -- mcause = soft.irq
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beq a1, a5, vec_machine_soft_handler
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li a5, MCAUSE_EXT_IRQ //0x8000000B -- mcause = ext.irq
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beq a1, a5, vec_machine_ext_handler
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mret
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#endif
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vec_machine_tmr_handler:
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csrr a1, mcause
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li a5, MCAUSE_TMR_IRQ //0x80000007 -- mcause = tmr.irq
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li a0, -1
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bne a1, a5, check_fail
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csrr t1, mip
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li t0, MIP_MTIP
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and t0, t1, t0
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beqz t0, check_fail
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#ifdef IPIC_ENABLED
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csrw IPIC_SOI, zero
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csrw IPIC_EOI, zero
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#endif
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_reset_mtimecmp
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csrr t1, mip
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andi t1, t1, MIP_MTIP
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bne t1, zero, check_fail
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addi t2, t2, 1 // tmr irq counter update
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mret
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vec_machine_ext_handler:
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csrr a1, mcause
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li a5, MCAUSE_EXT_IRQ //0x8000000B -- mcause = ext.irq
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li a0, -1
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bne a1, a5, check_fail
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csrr t1, mip
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li t0, MIP_MEIP
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and t0, t1, t0
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beqz t0, check_fail
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#ifdef IPIC_ENABLED
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csrw IPIC_SOI, zero
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csrw IPIC_EOI, zero
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#endif
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li t0, MEIE
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csrc mie, t0 // disable software interrupt
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li t0, TRIG_EXT_IRQ_ADDR
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li t1, EXT_IRQ_LINE_COMMON
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sh t1, (t0) // send command to disable external interrupt
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csrr t1, mip
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li t0, MIP_MEIP
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bne t1, zero, check_fail
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addi t2, t2, 1 // ext irq counter update
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mret
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vec_machine_soft_handler:
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csrr a1, mcause
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li a5, MCAUSE_SOFT_IRQ //0x80000003 -- mcause = soft.irq
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li a0, -1
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bne a1, a5, check_fail
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csrr t1, mip
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li t0, MIP_MSIP
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and t0, t1, t0
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beqz t0, check_fail
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#ifdef IPIC_ENABLED
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csrw IPIC_SOI, zero
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csrw IPIC_EOI, zero
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#endif
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li t0, MSIE
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csrc mie, t0 // disable software interrupt
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li t0, TRIG_SW_IRQ_ADDR
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li t1, 0x00000000
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sh t1, (t0) // send command to stop generating software interrupt
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li t0, MIP_MSIP
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csrc mip, t0
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csrr t1, mip
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li t0, MIP_MSIP
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and t1, t1, t0
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bne t1, zero, check_fail
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addi t2, t2, 1 // ext irq counter update
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mret
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check_fail:
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la t0, sc_exit
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jr t0
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_trap_fail:
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li a0, -1
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j check_fail
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