Init
This commit is contained in:
Mikhail Yenuchenko
819
sim/tests/common/riscv_macros.h
Normal file
819
sim/tests/common/riscv_macros.h
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// See LICENSE for license details.
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#ifndef __RISCV_MACROS_H
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#define __RISCV_MACROS_H
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#include "riscv_csr_encoding.h"
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#include "sc_test.h"
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//-----------------------------------------------------------------------
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// Begin Macro
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//-----------------------------------------------------------------------
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#define RVTEST_RV64U \
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.macro init; \
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.endm
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#define RVTEST_RV64UF \
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.macro init; \
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RVTEST_FP_ENABLE; \
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.endm
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#define RVTEST_RV32U \
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.macro init; \
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.endm
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#define RVTEST_RV32UF \
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.macro init; \
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RVTEST_FP_ENABLE; \
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.endm
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#define RVTEST_RV64M \
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.macro init; \
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RVTEST_ENABLE_MACHINE; \
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.endm
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#define RVTEST_RV64S \
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.macro init; \
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RVTEST_ENABLE_SUPERVISOR; \
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.endm
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#define RVTEST_RV32M \
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.macro init; \
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RVTEST_ENABLE_MACHINE; \
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.endm
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#define RVTEST_RV32S \
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.macro init; \
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RVTEST_ENABLE_SUPERVISOR; \
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.endm
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#if __riscv_xlen == 64
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# define CHECK_XLEN li a0, 1; slli a0, a0, 31; bgez a0, 1f; RVTEST_PASS; 1:
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#else
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# define CHECK_XLEN li a0, 1; slli a0, a0, 31; bltz a0, 1f; RVTEST_PASS; 1:
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#endif
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#define INIT_PMP \
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la t0, 1f; \
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csrw mtvec, t0; \
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li t0, -1; /* Set up a PMP to permit all accesses */ \
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csrw pmpaddr0, t0; \
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li t0, PMP_NAPOT | PMP_R | PMP_W | PMP_X; \
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csrw pmpcfg0, t0; \
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.balign 4; \
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1:
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#define INIT_SPTBR \
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la t0, 1f; \
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csrw mtvec, t0; \
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csrwi sptbr, 0; \
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.balign 4; \
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1:
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#define DELEGATE_NO_TRAPS
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#define RVTEST_ENABLE_SUPERVISOR \
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li a0, MSTATUS_MPP & (MSTATUS_MPP >> 1); \
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csrs mstatus, a0; \
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li a0, SIP_SSIP | SIP_STIP; \
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csrs mideleg, a0; \
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#define RVTEST_ENABLE_MACHINE \
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li a0, MSTATUS_MPP; \
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csrs mstatus, a0; \
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#define RVTEST_FP_ENABLE \
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li a0, MSTATUS_FS & (MSTATUS_FS >> 1); \
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csrs mstatus, a0; \
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csrwi fcsr, 0
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#define RISCV_MULTICORE_DISABLE \
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csrr a0, mhartid; \
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1: bnez a0, 1b
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#define EXTRA_TVEC_USER
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#define EXTRA_TVEC_SUPERVISOR
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#define EXTRA_TVEC_HYPERVISOR
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#define EXTRA_TVEC_MACHINE
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#define EXTRA_INIT
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#define EXTRA_INIT_TIMER
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#define INTERRUPT_HANDLER j other_exception /* No interrupts should occur */
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#define RVTEST_CODE_BEGIN \
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.section .text.init; \
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.org 0xC0, 0x00; \
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.balign 64; \
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.weak stvec_handler; \
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.weak mtvec_handler; \
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trap_vector: \
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/* test whether the test came from pass/fail */ \
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csrr a4, mcause; \
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li a5, CAUSE_USER_ECALL; \
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beq a4, a5, _report; \
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li a5, CAUSE_SUPERVISOR_ECALL; \
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beq a4, a5, _report; \
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li a5, CAUSE_MACHINE_ECALL; \
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beq a4, a5, _report; \
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/* if an mtvec_handler is defined, jump to it */ \
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la a4, mtvec_handler; \
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beqz a4, 1f; \
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jr a4; \
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/* was it an interrupt or an exception? */ \
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1: csrr a4, mcause; \
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bgez a4, handle_exception; \
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INTERRUPT_HANDLER; \
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handle_exception: \
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/* we don't know how to handle whatever the exception was */ \
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other_exception: \
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/* some unhandlable exception occurred */ \
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li a0, 0x1; \
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_report: \
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j sc_exit; \
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.balign 64; \
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.globl _start; \
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_start: \
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RISCV_MULTICORE_DISABLE; \
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/*INIT_SPTBR;*/ \
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/*INIT_PMP;*/ \
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DELEGATE_NO_TRAPS; \
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li TESTNUM, 0; \
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la t0, trap_vector; \
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csrw mtvec, t0; \
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CHECK_XLEN; \
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/* if an stvec_handler is defined, delegate exceptions to it */ \
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la t0, stvec_handler; \
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beqz t0, 1f; \
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csrw stvec, t0; \
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li t0, (1 << CAUSE_LOAD_PAGE_FAULT) | \
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(1 << CAUSE_STORE_PAGE_FAULT) | \
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(1 << CAUSE_FETCH_PAGE_FAULT) | \
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(1 << CAUSE_MISALIGNED_FETCH) | \
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(1 << CAUSE_USER_ECALL) | \
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(1 << CAUSE_BREAKPOINT); \
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csrw medeleg, t0; \
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csrr t1, medeleg; \
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bne t0, t1, other_exception; \
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1: csrwi mstatus, 0; \
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init; \
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EXTRA_INIT; \
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EXTRA_INIT_TIMER; \
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la t0, _run_test; \
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csrw mepc, t0; \
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csrr a0, mhartid; \
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mret; \
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.section .text; \
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_run_test:
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//-----------------------------------------------------------------------
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// End Macro
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//-----------------------------------------------------------------------
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#define RVTEST_CODE_END ecall: ecall
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//-----------------------------------------------------------------------
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// Pass/Fail Macro
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//-----------------------------------------------------------------------
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#define RVTEST_PASS \
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fence; \
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mv a1, TESTNUM; \
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li a0, 0x0; \
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ecall
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#define TESTNUM x28
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#define RVTEST_FAIL \
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fence; \
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mv a1, TESTNUM; \
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li a0, 0x1; \
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ecall
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//-----------------------------------------------------------------------
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// Data Section Macro
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//-----------------------------------------------------------------------
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#define EXTRA_DATA
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#define RVTEST_DATA_BEGIN \
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EXTRA_DATA \
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.pushsection .tohost,"aw",@progbits; \
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.balign 64; .global tohost; tohost: .dword 0; \
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.balign 64; .global fromhost; fromhost: .dword 0; \
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.popsection; \
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.balign 16; \
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.global begin_regstate; begin_regstate: .dword 0; .dword 0; .dword 0; \
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.balign 16; \
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.global begin_signature; begin_signature:
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#define RVTEST_DATA_END .balign 16; .global end_signature; end_signature:
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#-----------------------------------------------------------------------
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# Helper macros
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#-----------------------------------------------------------------------
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#define MASK_XLEN(x) ((x) & ((1 << (__riscv_xlen - 1) << 1) - 1))
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#define TEST_CASE( testnum, testreg, correctval, code... ) \
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test_ ## testnum: \
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code; \
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li x29, MASK_XLEN(correctval); \
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li TESTNUM, testnum; \
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bne testreg, x29, fail;
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# We use a macro hack to simpify code generation for various numbers
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# of bubble cycles.
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#define TEST_INSERT_NOPS_0
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#define TEST_INSERT_NOPS_1 nop; TEST_INSERT_NOPS_0
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#define TEST_INSERT_NOPS_2 nop; TEST_INSERT_NOPS_1
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#define TEST_INSERT_NOPS_3 nop; TEST_INSERT_NOPS_2
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#define TEST_INSERT_NOPS_4 nop; TEST_INSERT_NOPS_3
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#define TEST_INSERT_NOPS_5 nop; TEST_INSERT_NOPS_4
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#define TEST_INSERT_NOPS_6 nop; TEST_INSERT_NOPS_5
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#define TEST_INSERT_NOPS_7 nop; TEST_INSERT_NOPS_6
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#define TEST_INSERT_NOPS_8 nop; TEST_INSERT_NOPS_7
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#define TEST_INSERT_NOPS_9 nop; TEST_INSERT_NOPS_8
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#define TEST_INSERT_NOPS_10 nop; TEST_INSERT_NOPS_9
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#-----------------------------------------------------------------------
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# RV64UI MACROS
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#-----------------------------------------------------------------------
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#-----------------------------------------------------------------------
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# Tests for instructions with immediate operand
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#-----------------------------------------------------------------------
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#define SEXT_IMM(x) ((x) | (-(((x) >> 11) & 1) << 11))
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#define TEST_IMM_OP( testnum, inst, result, val1, imm ) \
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TEST_CASE( testnum, x3, result, \
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li x1, MASK_XLEN(val1); \
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inst x3, x1, SEXT_IMM(imm); \
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)
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#define TEST_IMM_OP_RVC( testnum, inst, result, val1, imm ) \
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TEST_CASE( testnum, x1, result, \
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li x1, val1; \
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inst x1, imm; \
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)
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#define TEST_IMM_SRC1_EQ_DEST( testnum, inst, result, val1, imm ) \
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TEST_CASE( testnum, x1, result, \
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li x1, MASK_XLEN(val1); \
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inst x1, x1, SEXT_IMM(imm); \
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)
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#define TEST_IMM_DEST_BYPASS( testnum, nop_cycles, inst, result, val1, imm ) \
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TEST_CASE( testnum, x6, result, \
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li x4, 0; \
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1: li x1, MASK_XLEN(val1); \
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inst x3, x1, SEXT_IMM(imm); \
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TEST_INSERT_NOPS_ ## nop_cycles \
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addi x6, x3, 0; \
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addi x4, x4, 1; \
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li x5, 2; \
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bne x4, x5, 1b \
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)
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#define TEST_IMM_SRC1_BYPASS( testnum, nop_cycles, inst, result, val1, imm ) \
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TEST_CASE( testnum, x3, result, \
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li x4, 0; \
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1: li x1, MASK_XLEN(val1); \
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TEST_INSERT_NOPS_ ## nop_cycles \
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inst x3, x1, SEXT_IMM(imm); \
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addi x4, x4, 1; \
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li x5, 2; \
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bne x4, x5, 1b \
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)
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#define TEST_IMM_ZEROSRC1( testnum, inst, result, imm ) \
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TEST_CASE( testnum, x1, result, \
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inst x1, x0, SEXT_IMM(imm); \
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)
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#define TEST_IMM_ZERODEST( testnum, inst, val1, imm ) \
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TEST_CASE( testnum, x0, 0, \
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li x1, MASK_XLEN(val1); \
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inst x0, x1, SEXT_IMM(imm); \
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)
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#-----------------------------------------------------------------------
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# Tests for vector config instructions
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#-----------------------------------------------------------------------
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#define TEST_VSETCFGIVL( testnum, nxpr, nfpr, bank, vl, result ) \
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TEST_CASE( testnum, x1, result, \
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li x1, (bank << 12); \
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vsetcfg x1,nxpr,nfpr; \
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li x1, vl; \
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vsetvl x1,x1; \
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)
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#define TEST_VVCFG( testnum, nxpr, nfpr, bank, vl, result ) \
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TEST_CASE( testnum, x1, result, \
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li x1, (bank << 12) | (nfpr << 6) | nxpr; \
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vsetcfg x1; \
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li x1, vl; \
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vsetvl x1,x1; \
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)
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#define TEST_VSETVL( testnum, nxpr, nfpr, bank, vl, result ) \
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TEST_CASE( testnum, x1, result, \
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li x1, (bank << 12); \
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vsetcfg x1,nxpr,nfpr; \
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li x1, vl; \
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vsetvl x1, x1; \
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)
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#-----------------------------------------------------------------------
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# Tests for an instruction with register operands
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#-----------------------------------------------------------------------
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#define TEST_R_OP( testnum, inst, result, val1 ) \
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TEST_CASE( testnum, x3, result, \
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li x1, val1; \
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inst x3, x1; \
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)
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#define TEST_R_SRC1_EQ_DEST( testnum, inst, result, val1 ) \
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TEST_CASE( testnum, x1, result, \
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li x1, val1; \
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inst x1, x1; \
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)
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#define TEST_R_DEST_BYPASS( testnum, nop_cycles, inst, result, val1 ) \
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TEST_CASE( testnum, x6, result, \
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li x4, 0; \
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1: li x1, val1; \
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inst x3, x1; \
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TEST_INSERT_NOPS_ ## nop_cycles \
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addi x6, x3, 0; \
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addi x4, x4, 1; \
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li x5, 2; \
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bne x4, x5, 1b \
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)
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#-----------------------------------------------------------------------
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# Tests for an instruction with register-register operands
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#-----------------------------------------------------------------------
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#define TEST_RR_OP( testnum, inst, result, val1, val2 ) \
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TEST_CASE( testnum, x3, result, \
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li x1, MASK_XLEN(val1); \
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li x2, MASK_XLEN(val2); \
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inst x3, x1, x2; \
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)
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#define TEST_RR_SRC1_EQ_DEST( testnum, inst, result, val1, val2 ) \
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TEST_CASE( testnum, x1, result, \
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li x1, MASK_XLEN(val1); \
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li x2, MASK_XLEN(val2); \
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inst x1, x1, x2; \
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)
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#define TEST_RR_SRC2_EQ_DEST( testnum, inst, result, val1, val2 ) \
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TEST_CASE( testnum, x2, result, \
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li x1, MASK_XLEN(val1); \
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li x2, MASK_XLEN(val2); \
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inst x2, x1, x2; \
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)
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#define TEST_RR_SRC12_EQ_DEST( testnum, inst, result, val1 ) \
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TEST_CASE( testnum, x1, result, \
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li x1, MASK_XLEN(val1); \
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inst x1, x1, x1; \
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)
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#define TEST_RR_DEST_BYPASS( testnum, nop_cycles, inst, result, val1, val2 ) \
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TEST_CASE( testnum, x6, result, \
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li x4, 0; \
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1: li x1, MASK_XLEN(val1); \
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li x2, MASK_XLEN(val2); \
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inst x3, x1, x2; \
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TEST_INSERT_NOPS_ ## nop_cycles \
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addi x6, x3, 0; \
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addi x4, x4, 1; \
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li x5, 2; \
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bne x4, x5, 1b \
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)
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#define TEST_RR_SRC12_BYPASS( testnum, src1_nops, src2_nops, inst, result, val1, val2 ) \
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TEST_CASE( testnum, x3, result, \
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li x4, 0; \
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1: li x1, MASK_XLEN(val1); \
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TEST_INSERT_NOPS_ ## src1_nops \
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li x2, MASK_XLEN(val2); \
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TEST_INSERT_NOPS_ ## src2_nops \
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inst x3, x1, x2; \
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addi x4, x4, 1; \
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li x5, 2; \
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bne x4, x5, 1b \
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)
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#define TEST_RR_SRC21_BYPASS( testnum, src1_nops, src2_nops, inst, result, val1, val2 ) \
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TEST_CASE( testnum, x3, result, \
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li x4, 0; \
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1: li x2, MASK_XLEN(val2); \
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TEST_INSERT_NOPS_ ## src1_nops \
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li x1, MASK_XLEN(val1); \
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TEST_INSERT_NOPS_ ## src2_nops \
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inst x3, x1, x2; \
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addi x4, x4, 1; \
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li x5, 2; \
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bne x4, x5, 1b \
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)
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#define TEST_RR_ZEROSRC1( testnum, inst, result, val ) \
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TEST_CASE( testnum, x2, result, \
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li x1, MASK_XLEN(val); \
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inst x2, x0, x1; \
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)
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#define TEST_RR_ZEROSRC2( testnum, inst, result, val ) \
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TEST_CASE( testnum, x2, result, \
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li x1, MASK_XLEN(val); \
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inst x2, x1, x0; \
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)
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#define TEST_RR_ZEROSRC12( testnum, inst, result ) \
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TEST_CASE( testnum, x1, result, \
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inst x1, x0, x0; \
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)
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#define TEST_RR_ZERODEST( testnum, inst, val1, val2 ) \
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TEST_CASE( testnum, x0, 0, \
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li x1, MASK_XLEN(val1); \
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li x2, MASK_XLEN(val2); \
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inst x0, x1, x2; \
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)
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#-----------------------------------------------------------------------
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# Test memory instructions
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#-----------------------------------------------------------------------
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|
||||
#define TEST_LD_OP( testnum, inst, result, offset, base ) \
|
||||
TEST_CASE( testnum, x3, result, \
|
||||
la x1, base; \
|
||||
inst x3, offset(x1); \
|
||||
)
|
||||
|
||||
#define TEST_ST_OP( testnum, load_inst, store_inst, result, offset, base ) \
|
||||
TEST_CASE( testnum, x3, result, \
|
||||
la x1, base; \
|
||||
li x2, result; \
|
||||
store_inst x2, offset(x1); \
|
||||
load_inst x3, offset(x1); \
|
||||
)
|
||||
|
||||
#define TEST_LD_DEST_BYPASS( testnum, nop_cycles, inst, result, offset, base ) \
|
||||
test_ ## testnum: \
|
||||
li TESTNUM, testnum; \
|
||||
li x4, 0; \
|
||||
1: la x1, base; \
|
||||
inst x3, offset(x1); \
|
||||
TEST_INSERT_NOPS_ ## nop_cycles \
|
||||
addi x6, x3, 0; \
|
||||
li x29, result; \
|
||||
bne x6, x29, fail; \
|
||||
addi x4, x4, 1; \
|
||||
li x5, 2; \
|
||||
bne x4, x5, 1b; \
|
||||
|
||||
#define TEST_LD_SRC1_BYPASS( testnum, nop_cycles, inst, result, offset, base ) \
|
||||
test_ ## testnum: \
|
||||
li TESTNUM, testnum; \
|
||||
li x4, 0; \
|
||||
1: la x1, base; \
|
||||
TEST_INSERT_NOPS_ ## nop_cycles \
|
||||
inst x3, offset(x1); \
|
||||
li x29, result; \
|
||||
bne x3, x29, fail; \
|
||||
addi x4, x4, 1; \
|
||||
li x5, 2; \
|
||||
bne x4, x5, 1b \
|
||||
|
||||
#define TEST_ST_SRC12_BYPASS( testnum, src1_nops, src2_nops, load_inst, store_inst, result, offset, base ) \
|
||||
test_ ## testnum: \
|
||||
li TESTNUM, testnum; \
|
||||
li x4, 0; \
|
||||
1: li x1, result; \
|
||||
TEST_INSERT_NOPS_ ## src1_nops \
|
||||
la x2, base; \
|
||||
TEST_INSERT_NOPS_ ## src2_nops \
|
||||
store_inst x1, offset(x2); \
|
||||
load_inst x3, offset(x2); \
|
||||
li x29, result; \
|
||||
bne x3, x29, fail; \
|
||||
addi x4, x4, 1; \
|
||||
li x5, 2; \
|
||||
bne x4, x5, 1b \
|
||||
|
||||
#define TEST_ST_SRC21_BYPASS( testnum, src1_nops, src2_nops, load_inst, store_inst, result, offset, base ) \
|
||||
test_ ## testnum: \
|
||||
li TESTNUM, testnum; \
|
||||
li x4, 0; \
|
||||
1: la x2, base; \
|
||||
TEST_INSERT_NOPS_ ## src1_nops \
|
||||
li x1, result; \
|
||||
TEST_INSERT_NOPS_ ## src2_nops \
|
||||
store_inst x1, offset(x2); \
|
||||
load_inst x3, offset(x2); \
|
||||
li x29, result; \
|
||||
bne x3, x29, fail; \
|
||||
addi x4, x4, 1; \
|
||||
li x5, 2; \
|
||||
bne x4, x5, 1b \
|
||||
|
||||
#-----------------------------------------------------------------------
|
||||
# Test branch instructions
|
||||
#-----------------------------------------------------------------------
|
||||
|
||||
#define TEST_BR1_OP_TAKEN( testnum, inst, val1 ) \
|
||||
test_ ## testnum: \
|
||||
li TESTNUM, testnum; \
|
||||
li x1, val1; \
|
||||
inst x1, 2f; \
|
||||
bne x0, TESTNUM, fail; \
|
||||
1: bne x0, TESTNUM, 3f; \
|
||||
2: inst x1, 1b; \
|
||||
bne x0, TESTNUM, fail; \
|
||||
3:
|
||||
|
||||
#define TEST_BR1_OP_NOTTAKEN( testnum, inst, val1 ) \
|
||||
test_ ## testnum: \
|
||||
li TESTNUM, testnum; \
|
||||
li x1, val1; \
|
||||
inst x1, 1f; \
|
||||
bne x0, TESTNUM, 2f; \
|
||||
1: bne x0, TESTNUM, fail; \
|
||||
2: inst x1, 1b; \
|
||||
3:
|
||||
|
||||
#define TEST_BR1_SRC1_BYPASS( testnum, nop_cycles, inst, val1 ) \
|
||||
test_ ## testnum: \
|
||||
li TESTNUM, testnum; \
|
||||
li x4, 0; \
|
||||
1: li x1, val1; \
|
||||
TEST_INSERT_NOPS_ ## nop_cycles \
|
||||
inst x1, fail; \
|
||||
addi x4, x4, 1; \
|
||||
li x5, 2; \
|
||||
bne x4, x5, 1b \
|
||||
|
||||
#define TEST_BR2_OP_TAKEN( testnum, inst, val1, val2 ) \
|
||||
test_ ## testnum: \
|
||||
li TESTNUM, testnum; \
|
||||
li x1, val1; \
|
||||
li x2, val2; \
|
||||
inst x1, x2, 2f; \
|
||||
bne x0, TESTNUM, fail; \
|
||||
1: bne x0, TESTNUM, 3f; \
|
||||
2: inst x1, x2, 1b; \
|
||||
bne x0, TESTNUM, fail; \
|
||||
3:
|
||||
|
||||
#define TEST_BR2_OP_NOTTAKEN( testnum, inst, val1, val2 ) \
|
||||
test_ ## testnum: \
|
||||
li TESTNUM, testnum; \
|
||||
li x1, val1; \
|
||||
li x2, val2; \
|
||||
inst x1, x2, 1f; \
|
||||
bne x0, TESTNUM, 2f; \
|
||||
1: bne x0, TESTNUM, fail; \
|
||||
2: inst x1, x2, 1b; \
|
||||
3:
|
||||
|
||||
#define TEST_BR2_SRC12_BYPASS( testnum, src1_nops, src2_nops, inst, val1, val2 ) \
|
||||
test_ ## testnum: \
|
||||
li TESTNUM, testnum; \
|
||||
li x4, 0; \
|
||||
1: li x1, val1; \
|
||||
TEST_INSERT_NOPS_ ## src1_nops \
|
||||
li x2, val2; \
|
||||
TEST_INSERT_NOPS_ ## src2_nops \
|
||||
inst x1, x2, fail; \
|
||||
addi x4, x4, 1; \
|
||||
li x5, 2; \
|
||||
bne x4, x5, 1b \
|
||||
|
||||
#define TEST_BR2_SRC21_BYPASS( testnum, src1_nops, src2_nops, inst, val1, val2 ) \
|
||||
test_ ## testnum: \
|
||||
li TESTNUM, testnum; \
|
||||
li x4, 0; \
|
||||
1: li x2, val2; \
|
||||
TEST_INSERT_NOPS_ ## src1_nops \
|
||||
li x1, val1; \
|
||||
TEST_INSERT_NOPS_ ## src2_nops \
|
||||
inst x1, x2, fail; \
|
||||
addi x4, x4, 1; \
|
||||
li x5, 2; \
|
||||
bne x4, x5, 1b \
|
||||
|
||||
#-----------------------------------------------------------------------
|
||||
# Test jump instructions
|
||||
#-----------------------------------------------------------------------
|
||||
|
||||
#define TEST_JR_SRC1_BYPASS( testnum, nop_cycles, inst ) \
|
||||
test_ ## testnum: \
|
||||
li TESTNUM, testnum; \
|
||||
li x4, 0; \
|
||||
1: la x6, 2f; \
|
||||
TEST_INSERT_NOPS_ ## nop_cycles \
|
||||
inst x6; \
|
||||
bne x0, TESTNUM, fail; \
|
||||
2: addi x4, x4, 1; \
|
||||
li x5, 2; \
|
||||
bne x4, x5, 1b \
|
||||
|
||||
#define TEST_JALR_SRC1_BYPASS( testnum, nop_cycles, inst ) \
|
||||
test_ ## testnum: \
|
||||
li TESTNUM, testnum; \
|
||||
li x4, 0; \
|
||||
1: la x6, 2f; \
|
||||
TEST_INSERT_NOPS_ ## nop_cycles \
|
||||
inst x19, x6, 0; \
|
||||
bne x0, TESTNUM, fail; \
|
||||
2: addi x4, x4, 1; \
|
||||
li x5, 2; \
|
||||
bne x4, x5, 1b \
|
||||
|
||||
|
||||
#-----------------------------------------------------------------------
|
||||
# RV64UF MACROS
|
||||
#-----------------------------------------------------------------------
|
||||
|
||||
#-----------------------------------------------------------------------
|
||||
# Tests floating-point instructions
|
||||
#-----------------------------------------------------------------------
|
||||
|
||||
#define qNaNf 0f:7fc00000
|
||||
#define sNaNf 0f:7f800001
|
||||
#define qNaN 0d:7ff8000000000000
|
||||
#define sNaN 0d:7ff0000000000001
|
||||
|
||||
#define TEST_FP_OP_S_INTERNAL( testnum, flags, result, val1, val2, val3, code... ) \
|
||||
test_ ## testnum: \
|
||||
li TESTNUM, testnum; \
|
||||
la a0, test_ ## testnum ## _data ;\
|
||||
flw f0, 0(a0); \
|
||||
flw f1, 4(a0); \
|
||||
flw f2, 8(a0); \
|
||||
lw a3, 12(a0); \
|
||||
code; \
|
||||
fsflags a1, x0; \
|
||||
li a2, flags; \
|
||||
bne a0, a3, fail; \
|
||||
bne a1, a2, fail; \
|
||||
j 2f; \
|
||||
.balign 4; \
|
||||
.data; \
|
||||
test_ ## testnum ## _data: \
|
||||
.float val1; \
|
||||
.float val2; \
|
||||
.float val3; \
|
||||
.result; \
|
||||
.text; \
|
||||
2:
|
||||
|
||||
#define TEST_FP_OP_D_INTERNAL( testnum, flags, result, val1, val2, val3, code... ) \
|
||||
test_ ## testnum: \
|
||||
li TESTNUM, testnum; \
|
||||
la a0, test_ ## testnum ## _data ;\
|
||||
fld f0, 0(a0); \
|
||||
fld f1, 8(a0); \
|
||||
fld f2, 16(a0); \
|
||||
ld a3, 24(a0); \
|
||||
code; \
|
||||
fsflags a1, x0; \
|
||||
li a2, flags; \
|
||||
bne a0, a3, fail; \
|
||||
bne a1, a2, fail; \
|
||||
j 2f; \
|
||||
.data; \
|
||||
.balign 8; \
|
||||
test_ ## testnum ## _data: \
|
||||
.double val1; \
|
||||
.double val2; \
|
||||
.double val3; \
|
||||
.result; \
|
||||
.text; \
|
||||
2:
|
||||
|
||||
#define TEST_FCVT_S_D( testnum, result, val1 ) \
|
||||
TEST_FP_OP_D_INTERNAL( testnum, 0, double result, val1, 0.0, 0.0, \
|
||||
fcvt.s.d f3, f0; fcvt.d.s f3, f3; fmv.x.d a0, f3)
|
||||
|
||||
#define TEST_FCVT_D_S( testnum, result, val1 ) \
|
||||
TEST_FP_OP_S_INTERNAL( testnum, 0, float result, val1, 0.0, 0.0, \
|
||||
fcvt.d.s f3, f0; fcvt.s.d f3, f3; fmv.x.s a0, f3)
|
||||
|
||||
#define TEST_FP_OP1_S( testnum, inst, flags, result, val1 ) \
|
||||
TEST_FP_OP_S_INTERNAL( testnum, flags, float result, val1, 0.0, 0.0, \
|
||||
inst f3, f0; fmv.x.s a0, f3)
|
||||
|
||||
#define TEST_FP_OP1_D( testnum, inst, flags, result, val1 ) \
|
||||
TEST_FP_OP_D_INTERNAL( testnum, flags, double result, val1, 0.0, 0.0, \
|
||||
inst f3, f0; fmv.x.d a0, f3)
|
||||
|
||||
#define TEST_FP_OP1_S_DWORD_RESULT( testnum, inst, flags, result, val1 ) \
|
||||
TEST_FP_OP_S_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \
|
||||
inst f3, f0; fmv.x.s a0, f3)
|
||||
|
||||
#define TEST_FP_OP1_D_DWORD_RESULT( testnum, inst, flags, result, val1 ) \
|
||||
TEST_FP_OP_D_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \
|
||||
inst f3, f0; fmv.x.d a0, f3)
|
||||
|
||||
#define TEST_FP_OP2_S( testnum, inst, flags, result, val1, val2 ) \
|
||||
TEST_FP_OP_S_INTERNAL( testnum, flags, float result, val1, val2, 0.0, \
|
||||
inst f3, f0, f1; fmv.x.s a0, f3)
|
||||
|
||||
#define TEST_FP_OP2_D( testnum, inst, flags, result, val1, val2 ) \
|
||||
TEST_FP_OP_D_INTERNAL( testnum, flags, double result, val1, val2, 0.0, \
|
||||
inst f3, f0, f1; fmv.x.d a0, f3)
|
||||
|
||||
#define TEST_FP_OP3_S( testnum, inst, flags, result, val1, val2, val3 ) \
|
||||
TEST_FP_OP_S_INTERNAL( testnum, flags, float result, val1, val2, val3, \
|
||||
inst f3, f0, f1, f2; fmv.x.s a0, f3)
|
||||
|
||||
#define TEST_FP_OP3_D( testnum, inst, flags, result, val1, val2, val3 ) \
|
||||
TEST_FP_OP_D_INTERNAL( testnum, flags, double result, val1, val2, val3, \
|
||||
inst f3, f0, f1, f2; fmv.x.d a0, f3)
|
||||
|
||||
#define TEST_FP_INT_OP_S( testnum, inst, flags, result, val1, rm ) \
|
||||
TEST_FP_OP_S_INTERNAL( testnum, flags, word result, val1, 0.0, 0.0, \
|
||||
inst a0, f0, rm)
|
||||
|
||||
#define TEST_FP_INT_OP_D( testnum, inst, flags, result, val1, rm ) \
|
||||
TEST_FP_OP_D_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \
|
||||
inst a0, f0, rm)
|
||||
|
||||
#define TEST_FP_CMP_OP_S( testnum, inst, flags, result, val1, val2 ) \
|
||||
TEST_FP_OP_S_INTERNAL( testnum, flags, word result, val1, val2, 0.0, \
|
||||
inst a0, f0, f1)
|
||||
|
||||
#define TEST_FP_CMP_OP_D( testnum, inst, flags, result, val1, val2 ) \
|
||||
TEST_FP_OP_D_INTERNAL( testnum, flags, dword result, val1, val2, 0.0, \
|
||||
inst a0, f0, f1)
|
||||
|
||||
#define TEST_FCLASS_S(testnum, correct, input) \
|
||||
TEST_CASE(testnum, a0, correct, li a0, input; fmv.s.x fa0, a0; \
|
||||
fclass.s a0, fa0)
|
||||
|
||||
#define TEST_FCLASS_D(testnum, correct, input) \
|
||||
TEST_CASE(testnum, a0, correct, li a0, input; fmv.d.x fa0, a0; \
|
||||
fclass.d a0, fa0)
|
||||
|
||||
#define TEST_INT_FP_OP_S( testnum, inst, result, val1 ) \
|
||||
test_ ## testnum: \
|
||||
li TESTNUM, testnum; \
|
||||
la a0, test_ ## testnum ## _data ;\
|
||||
lw a3, 0(a0); \
|
||||
li a0, val1; \
|
||||
inst f0, a0; \
|
||||
fsflags x0; \
|
||||
fmv.x.s a0, f0; \
|
||||
bne a0, a3, fail; \
|
||||
j 1f; \
|
||||
.balign 4; \
|
||||
test_ ## testnum ## _data: \
|
||||
.float result; \
|
||||
1:
|
||||
|
||||
#define TEST_INT_FP_OP_D( testnum, inst, result, val1 ) \
|
||||
test_ ## testnum: \
|
||||
li TESTNUM, testnum; \
|
||||
la a0, test_ ## testnum ## _data ;\
|
||||
ld a3, 0(a0); \
|
||||
li a0, val1; \
|
||||
inst f0, a0; \
|
||||
fsflags x0; \
|
||||
fmv.x.d a0, f0; \
|
||||
bne a0, a3, fail; \
|
||||
j 1f; \
|
||||
.balign 8; \
|
||||
test_ ## testnum ## _data: \
|
||||
.double result; \
|
||||
1:
|
||||
|
||||
#-----------------------------------------------------------------------
|
||||
# Pass and fail code (assumes test num is in TESTNUM)
|
||||
#-----------------------------------------------------------------------
|
||||
|
||||
#define TEST_PASSFAIL \
|
||||
bne x0, TESTNUM, pass; \
|
||||
fail: \
|
||||
RVTEST_FAIL; \
|
||||
pass: \
|
||||
RVTEST_PASS \
|
||||
|
||||
|
||||
#-----------------------------------------------------------------------
|
||||
# Test data section
|
||||
#-----------------------------------------------------------------------
|
||||
|
||||
#define TEST_DATA
|
||||
|
||||
#endif
|
||||
|
||||
Reference in New Issue
Block a user