From c466c49ab3241fd151544fcb2e3d059cabca15a5 Mon Sep 17 00:00:00 2001 From: Mikhail Yenuchenko <76039929+mixeme@users.noreply.github.com> Date: Tue, 20 Jan 2026 17:15:38 +0300 Subject: [PATCH] Add tech files --- scripts/scripts_aux/XFAB180_MMMC.tcl | 87 ++++++++++++++++++++++++++++ scripts/scripts_aux/XFAB180_fast.tcl | 26 +++++++++ scripts/scripts_aux/XFAB180_slow.tcl | 26 +++++++++ scripts/scripts_aux/XFAB180_typ.tcl | 26 +++++++++ 4 files changed, 165 insertions(+) create mode 100644 scripts/scripts_aux/XFAB180_MMMC.tcl create mode 100644 scripts/scripts_aux/XFAB180_fast.tcl create mode 100644 scripts/scripts_aux/XFAB180_slow.tcl create mode 100644 scripts/scripts_aux/XFAB180_typ.tcl diff --git a/scripts/scripts_aux/XFAB180_MMMC.tcl b/scripts/scripts_aux/XFAB180_MMMC.tcl new file mode 100644 index 0000000..d259733 --- /dev/null +++ b/scripts/scripts_aux/XFAB180_MMMC.tcl @@ -0,0 +1,87 @@ +### Technology: "X-FAB 180 nm CMOS, XT018 1243" +### Library: "D_CELLS_HD, 1.8V" +### Tools: "Cadence Encounter" +### +### Stage: "PaR" +### File description: "Multi-mode multi-corner (MMMC) file for the Cadence Encounter EDA tool" + + +## Timing constraints file from the synthesis +create_constraint_mode -name CONSTRAINTS -sdc_files ${PAR_SDC_PATH}/${PAR_SDC_TOP_NAME} + + +## Create timing libraries sets +# The slowest corner +create_library_set -name SLOWlib \ +-timing {/Cadence/Libs/X_FAB/XKIT/xt018/diglibs/D_CELLS_HD/v4_0/liberty_LP5MOS/v4_0_0/PVT_1_80V_range/D_CELLS_HD_LP5MOS_slow_1_62V_175C.lib} + +# Typical corner +create_library_set -name TYPlib \ +-timing {/Cadence/Libs/X_FAB/XKIT/xt018/diglibs/D_CELLS_HD/v4_0/liberty_LP5MOS/v4_0_0/PVT_1_80V_range/D_CELLS_HD_LP5MOS_typ_1_80V_25C.lib} + +# The fastest corner +create_library_set -name FASTlib \ +-timing {/Cadence/Libs/X_FAB/XKIT/xt018/diglibs/D_CELLS_HD/v4_0/liberty_LP5MOS/v4_0_0/PVT_1_80V_range/D_CELLS_HD_LP5MOS_fast_1_98V_m40C.lib} + + +## Create operating conditions (P-V-T) for the timing libraries (CAN BE ABSENT IF CONDITIONS ARE GENERAL) +# The slowest operation condition +create_op_cond -name PVT_slow_1_62V_175C \ +-library_file {/Cadence/Libs/X_FAB/XKIT/xt018/diglibs/D_CELLS_HD/v4_0/liberty_LP5MOS/v4_0_0/PVT_1_80V_range/D_CELLS_HD_LP5MOS_slow_1_62V_175C.lib} \ +-P {1} -V {1.62} -T {175} + +# Typical operation condition +create_op_cond -name PVT_typ_1_80V_25C \ +-library_file {/Cadence/Libs/X_FAB/XKIT/xt018/diglibs/D_CELLS_HD/v4_0/liberty_LP5MOS/v4_0_0/PVT_1_80V_range/D_CELLS_HD_LP5MOS_typ_1_80V_25C.lib} \ +-P {1} -V {1.8} -T {25} + +# The fastest operation condition +create_op_cond -name PVT_fast_1_98V_-40C \ +-library_file {/Cadence/Libs/X_FAB/XKIT/xt018/diglibs/D_CELLS_HD/v4_0/liberty_LP5MOS/v4_0_0/PVT_1_80V_range/D_CELLS_HD_LP5MOS_fast_1_98V_m40C.lib} \ +-P {1} -V {1.98} -T {-40} + + +## Create RC corner(s) from capacitance table(s) +create_rc_corner -name RCcornerMIN \ +-cap_table /Cadence/Libs/X_FAB/XKIT/xt018/cadence/v7_0/capTbl/v7_0_1/xt018_xx43_MET4_METMID_METTHK_min.capTbl \ +-qx_tech_file /Cadence/Libs/X_FAB/XKIT/xt018/cadence/v7_0/QRC_pvs/v7_0_3/XT018_1243/QRC-Min/qrcTechFile + +create_rc_corner -name RCcornerTYP \ +-cap_table /Cadence/Libs/X_FAB/XKIT/xt018/cadence/v7_0/capTbl/v7_0_1/xt018_xx43_MET4_METMID_METTHK_typ.capTbl \ +-qx_tech_file /Cadence/Libs/X_FAB/XKIT/xt018/cadence/v7_0/QRC_pvs/v7_0_3/XT018_1243/QRC-Typ/qrcTechFile + +create_rc_corner -name RCcornerMAX \ +-cap_table /Cadence/Libs/X_FAB/XKIT/xt018/cadence/v7_0/capTbl/v7_0_1/xt018_xx43_MET4_METMID_METTHK_max.capTbl \ +-qx_tech_file /Cadence/Libs/X_FAB/XKIT/xt018/cadence/v7_0/QRC_pvs/v7_0_3/XT018_1243/QRC-Max/qrcTechFile + + +## Create delay corner(s) +create_delay_corner -name DELAYcornerSLOW \ +-library_set SLOWlib \ +-rc_corner RCcornerMAX + +create_delay_corner -name DELAYcornerTYP \ +-library_set TYPlib \ +-rc_corner RCcornerTYP + +create_delay_corner -name DELAYcornerFAST \ +-library_set FASTlib \ +-rc_corner RCcornerMIN + + +## Create analysis views +create_analysis_view -name MAXview \ +-delay_corner {DELAYcornerSLOW} \ +-constraint_mode {CONSTRAINTS} + +create_analysis_view -name TYPview \ +-delay_corner {DELAYcornerTYP} \ +-constraint_mode {CONSTRAINTS} + +create_analysis_view -name MINview \ +-delay_corner {DELAYcornerFAST} \ +-constraint_mode {CONSTRAINTS} + + +## Set analysis view to above for both setup and hold +set_analysis_view -setup {TYPview} -hold {TYPview} diff --git a/scripts/scripts_aux/XFAB180_fast.tcl b/scripts/scripts_aux/XFAB180_fast.tcl new file mode 100644 index 0000000..f0932ab --- /dev/null +++ b/scripts/scripts_aux/XFAB180_fast.tcl @@ -0,0 +1,26 @@ +### Technology: "X-FAB 180 nm CMOS, XT018 1243" +### Library: "D_CELLS_HD, 1.8V" +### Tools: "Cadence RTL Compiler" +### +### Stage: "Synthesis" +### File description: "Contains paths to the library of digital cells (slow corner)" + + +# Setup path for liberty CPF directory +set_attribute lib_search_path /Cadence/Libs/X_FAB/XKIT/xt018/diglibs/D_CELLS_HD/v4_0/liberty_LP5MOS/v4_0_0/PVT_1_80V_range + +# Setup PVT corner .lib file +set_attribute library {/Cadence/Libs/X_FAB/XKIT/xt018/diglibs/D_CELLS_HD/v4_0/liberty_LP5MOS/v4_0_0/PVT_1_80V_range/D_CELLS_HD_LP5MOS_fast_1_98V_m40C.lib} + +# Setup LEF files +set_attribute lef_library { \ +/Cadence/Libs/X_FAB/XKIT/xt018/cadence/v7_0/techLEF/v7_0_1_1/xt018_xx43_MET4_METMID_METTHK.lef \ +/Cadence/Libs/X_FAB/XKIT/xt018/diglibs/D_CELLS_HD/v4_0/LEF/v4_0_0/xt018_D_CELLS_HD.lef \ +/Cadence/Libs/X_FAB/XKIT/xt018/diglibs/D_CELLS_HD/v4_0/LEF/v4_0_0/xt018_xx43_MET4_METMID_METTHK_D_CELLS_HD_mprobe.lef \ +} + +# Setup capacitance table file +set_attribute cap_table_file /Cadence/Libs/X_FAB/XKIT/xt018/cadence/v7_0/capTbl/v7_0_1/xt018_xx43_MET4_METMID_METTHK_fast.capTbl + +# Setup error on blackbox +set_attribute hdl_error_on_blackbox true diff --git a/scripts/scripts_aux/XFAB180_slow.tcl b/scripts/scripts_aux/XFAB180_slow.tcl new file mode 100644 index 0000000..3ecc65a --- /dev/null +++ b/scripts/scripts_aux/XFAB180_slow.tcl @@ -0,0 +1,26 @@ +### Technology: "X-FAB 180 nm CMOS, XT018 1243" +### Library: "D_CELLS_HD, 1.8V" +### Tools: "Cadence RTL Compiler" +### +### Stage: "Synthesis" +### File description: "Contains paths to the library of digital cells (slow corner)" + + +# Setup path for liberty CPF directory +set_attribute lib_search_path /Cadence/Libs/X_FAB/XKIT/xt018/diglibs/D_CELLS_HD/v4_0/liberty_LP5MOS/v4_0_0/PVT_1_80V_range + +# Setup PVT corner .lib file +set_attribute library {/Cadence/Libs/X_FAB/XKIT/xt018/diglibs/D_CELLS_HD/v4_0/liberty_LP5MOS/v4_0_0/PVT_1_80V_range/D_CELLS_HD_LP5MOS_slow_1_62V_175C.lib} + +# Setup LEF files +set_attribute lef_library { \ +/Cadence/Libs/X_FAB/XKIT/xt018/cadence/v7_0/techLEF/v7_0_1_1/xt018_xx43_MET4_METMID_METTHK.lef \ +/Cadence/Libs/X_FAB/XKIT/xt018/diglibs/D_CELLS_HD/v4_0/LEF/v4_0_0/xt018_D_CELLS_HD.lef \ +/Cadence/Libs/X_FAB/XKIT/xt018/diglibs/D_CELLS_HD/v4_0/LEF/v4_0_0/xt018_xx43_MET4_METMID_METTHK_D_CELLS_HD_mprobe.lef \ +} + +# Setup capacitance table file +set_attribute cap_table_file /Cadence/Libs/X_FAB/XKIT/xt018/cadence/v7_0/capTbl/v7_0_1/xt018_xx43_MET4_METMID_METTHK_slow.capTbl + +# Setup error on blackbox +set_attribute hdl_error_on_blackbox true diff --git a/scripts/scripts_aux/XFAB180_typ.tcl b/scripts/scripts_aux/XFAB180_typ.tcl new file mode 100644 index 0000000..a0d06d1 --- /dev/null +++ b/scripts/scripts_aux/XFAB180_typ.tcl @@ -0,0 +1,26 @@ +### Technology: "X-FAB 180 nm CMOS, XT018 1243" +### Library: "D_CELLS_HD, 1.8V" +### Tools: "Cadence RTL Compiler" +### +### Stage: "Synthesis" +### File description: "Contains paths to the library of digital cells (slow corner)" + + +# Setup path for liberty CPF directory +set_attribute lib_search_path /Cadence/Libs/X_FAB/XKIT/xt018/diglibs/D_CELLS_HD/v4_0/liberty_LP5MOS/v4_0_0/PVT_1_80V_range + +# Setup PVT corner .lib file +set_attribute library {/Cadence/Libs/X_FAB/XKIT/xt018/diglibs/D_CELLS_HD/v4_0/liberty_LP5MOS/v4_0_0/PVT_1_80V_range/D_CELLS_HD_LP5MOS_typ_1_80V_25C.lib} + +# Setup LEF files +set_attribute lef_library { \ +/Cadence/Libs/X_FAB/XKIT/xt018/cadence/v7_0/techLEF/v7_0_1_1/xt018_xx43_MET4_METMID_METTHK.lef \ +/Cadence/Libs/X_FAB/XKIT/xt018/diglibs/D_CELLS_HD/v4_0/LEF/v4_0_0/xt018_D_CELLS_HD.lef \ +/Cadence/Libs/X_FAB/XKIT/xt018/diglibs/D_CELLS_HD/v4_0/LEF/v4_0_0/xt018_xx43_MET4_METMID_METTHK_D_CELLS_HD_mprobe.lef \ +} + +# Setup capacitance table file +set_attribute cap_table_file /Cadence/Libs/X_FAB/XKIT/xt018/cadence/v7_0/capTbl/v7_0_1/xt018_xx43_MET4_METMID_METTHK_typ.capTbl + +# Setup error on blackbox +set_attribute hdl_error_on_blackbox true