From 93720fe19604fb2e21d087b2e3f98138dacc0d79 Mon Sep 17 00:00:00 2001 From: Mikhail Yenuchenko <76039929+mixeme@users.noreply.github.com> Date: Tue, 20 Jan 2026 17:14:51 +0300 Subject: [PATCH] Create scr1_top_ahb.sdc --- src/sdc/scr1_top_ahb.sdc | 106 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 106 insertions(+) create mode 100644 src/sdc/scr1_top_ahb.sdc diff --git a/src/sdc/scr1_top_ahb.sdc b/src/sdc/scr1_top_ahb.sdc new file mode 100644 index 0000000..4444b23 --- /dev/null +++ b/src/sdc/scr1_top_ahb.sdc @@ -0,0 +1,106 @@ +### Stage: "Synthesis and PaR" +### File description: "Constraints for the design" + + +# SET LIB UNITS +set_units -time 1.0ns; +set_units -capacitance 1.0pF; + +set_max_capacitance 0.5 [all_outputs] + +### ====================== CLOCKS =========================== +#clock uncertainty: 200ps for all clocks +set CLK_UNCERT 0.2; +#transition: 1ns R/F + +# CLOCK PERIOD +set CLK_PERIOD 11.13 +set TCK_PERIOD 100 +set RTC_CLK_PERIOD 10000 + +# IO DELAYS +set INPUT_DELAY_CLK [expr $CLK_PERIOD/4.0] +set OUTPUT_DELAY_CLK [expr $CLK_PERIOD/4.0] + +set INPUT_DELAY_TCK [expr $TCK_PERIOD/4.0] +set OUTPUT_DELAY_TCK [expr $TCK_PERIOD/4.0] + +#clk->100MHz +create_clock -name "clk" -period $CLK_PERIOD -waveform "0 [expr $CLK_PERIOD/2.0]" [get_ports "clk"] +#tck->10MHz +create_clock -name "tck" -period $TCK_PERIOD -waveform "0 [expr $TCK_PERIOD/2.0]" [get_ports "tck"] +#rtc_clk->100kHz +create_clock -name "rtc_clk" -period $RTC_CLK_PERIOD -waveform "0 [expr $RTC_CLK_PERIOD/2.0]" [get_ports "rtc_clk"] + +set_clock_groups -asynchronous -group {"clk"} -group {"tck"} -group {"rtc_clk"} + +set MINRISE 0 +set MAXRISE 1.0 +set MINFALL 0 +set MAXFALL 1.0 + +set_clock_uncertainty $CLK_UNCERT [get_clocks "clk"] +set_clock_transition -rise -min $MINRISE [get_clocks "clk"] +set_clock_transition -rise -max $MAXRISE [get_clocks "clk"] +set_clock_transition -fall -min $MINFALL [get_clocks "clk"] +set_clock_transition -fall -max $MAXFALL [get_clocks "clk"] + +set_clock_uncertainty $CLK_UNCERT [get_clocks "tck"] +set_clock_transition -rise -min $MINRISE [get_clocks "tck"] +set_clock_transition -rise -max $MAXRISE [get_clocks "tck"] +set_clock_transition -fall -min $MINFALL [get_clocks "tck"] +set_clock_transition -fall -max $MAXFALL [get_clocks "tck"] + +set_clock_uncertainty $CLK_UNCERT [get_clocks "rtc_clk"] +set_clock_transition -rise -min $MINRISE [get_clocks "rtc_clk"] +set_clock_transition -rise -max $MAXRISE [get_clocks "rtc_clk"] +set_clock_transition -fall -min $MINFALL [get_clocks "rtc_clk"] +set_clock_transition -fall -max $MAXFALL [get_clocks "rtc_clk"] + + +set_ideal_network [get_ports "pwrup_rst_n"] +set_ideal_network [get_ports "rst_n"] +set_ideal_network [get_ports "cpu_rst_n"] +set_ideal_network [get_ports "test_rst_n"] +set_ideal_network [get_ports "trst_n"] + +set_false_path -from [get_ports "pwrup_rst_n"] +set_false_path -from [get_ports "rst_n"] +set_false_path -from [get_ports "cpu_rst_n"] +set_false_path -from [get_ports "test_rst_n"] +set_false_path -from [get_ports "trst_n"] + +#IO delays: + +set_input_delay -clock "clk" -max $INPUT_DELAY_CLK [remove_from_collection [all_inputs] {trst_n tdi tms}] +set_input_delay -clock "clk" -min $INPUT_DELAY_CLK [remove_from_collection [all_inputs] {trst_n tdi tms}] + +set_input_delay -clock "tck" -max $INPUT_DELAY_TCK [get_ports {trst_n tdi tms}] +set_input_delay -clock "tck" -min $INPUT_DELAY_TCK [get_ports {trst_n tdi tms}] + + +set_output_delay -clock "clk" -max $OUTPUT_DELAY_CLK [remove_from_collection [all_outputs] {tdo tdo_en}] +set_output_delay -clock "clk" -min $OUTPUT_DELAY_CLK [remove_from_collection [all_outputs] {tdo tdo_en}] + +set_output_delay -clock "tck" -max $OUTPUT_DELAY_TCK [get_ports {tdo tdo_en}] +set_output_delay -clock "tck" -min $OUTPUT_DELAY_TCK [get_ports {tdo tdo_en}] + + +set_case_analysis 0 [get_ports "test_mode"] + +# |--------------| +#->| |-> +#->| clk |-> +# | | +# ---------------- +# | rtc | +# ---------------- +#->| |->tdo +#->| tck |->tdo_en +# | | +# |--------------| + + + + +