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Mikhail Yenuchenko
271
src/rtl/scr1/scr1_timer.sv
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271
src/rtl/scr1/scr1_timer.sv
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/// Copyright by Syntacore LLC © 2016-2021. See LICENSE for details
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/// @file <scr1_timer.sv>
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/// @brief Memory-mapped Timer
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///
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`include "scr1_arch_description.svh"
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`include "scr1_memif.svh"
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module scr1_timer (
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// Common
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input logic rst_n,
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input logic clk,
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input logic rtc_clk,
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// Memory interface
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input logic dmem_req,
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input type_scr1_mem_cmd_e dmem_cmd,
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input type_scr1_mem_width_e dmem_width,
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input logic [`SCR1_DMEM_AWIDTH-1:0] dmem_addr,
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input logic [`SCR1_DMEM_DWIDTH-1:0] dmem_wdata,
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output logic dmem_req_ack,
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output logic [`SCR1_DMEM_DWIDTH-1:0] dmem_rdata,
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output type_scr1_mem_resp_e dmem_resp,
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// Timer interface
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output logic [63:0] timer_val,
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output logic timer_irq
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);
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//-------------------------------------------------------------------------------
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// Local parameters declaration
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//-------------------------------------------------------------------------------
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localparam int unsigned SCR1_TIMER_ADDR_WIDTH = 5;
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localparam logic [SCR1_TIMER_ADDR_WIDTH-1:0] SCR1_TIMER_CONTROL = 5'h0;
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localparam logic [SCR1_TIMER_ADDR_WIDTH-1:0] SCR1_TIMER_DIVIDER = 5'h4;
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localparam logic [SCR1_TIMER_ADDR_WIDTH-1:0] SCR1_TIMER_MTIMELO = 5'h8;
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localparam logic [SCR1_TIMER_ADDR_WIDTH-1:0] SCR1_TIMER_MTIMEHI = 5'hC;
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localparam logic [SCR1_TIMER_ADDR_WIDTH-1:0] SCR1_TIMER_MTIMECMPLO = 5'h10;
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localparam logic [SCR1_TIMER_ADDR_WIDTH-1:0] SCR1_TIMER_MTIMECMPHI = 5'h14;
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localparam int unsigned SCR1_TIMER_CONTROL_EN_OFFSET = 0;
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localparam int unsigned SCR1_TIMER_CONTROL_CLKSRC_OFFSET = 1;
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localparam int unsigned SCR1_TIMER_DIVIDER_WIDTH = 10;
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//-------------------------------------------------------------------------------
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// Local signals declaration
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//-------------------------------------------------------------------------------
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logic [63:0] mtime_reg;
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logic [63:0] mtime_new;
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logic [63:0] mtimecmp_reg;
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logic [63:0] mtimecmp_new;
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logic timer_en;
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logic timer_clksrc_rtc;
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logic [SCR1_TIMER_DIVIDER_WIDTH-1:0] timer_div;
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logic control_up;
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logic divider_up;
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logic mtimelo_up;
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logic mtimehi_up;
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logic mtimecmplo_up;
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logic mtimecmphi_up;
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logic dmem_req_valid;
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logic [3:0] rtc_sync;
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logic rtc_ext_pulse;
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logic [SCR1_TIMER_DIVIDER_WIDTH-1:0] timeclk_cnt;
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logic timeclk_cnt_en;
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logic time_posedge;
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logic time_cmp_flag;
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//-------------------------------------------------------------------------------
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// Registers
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//-------------------------------------------------------------------------------
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// CONTROL
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always_ff @(posedge clk, negedge rst_n) begin
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if (~rst_n) begin
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timer_en <= 1'b1;
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timer_clksrc_rtc <= 1'b0;
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end else begin
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if (control_up) begin
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timer_en <= dmem_wdata[SCR1_TIMER_CONTROL_EN_OFFSET];
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timer_clksrc_rtc <= dmem_wdata[SCR1_TIMER_CONTROL_CLKSRC_OFFSET];
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end
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end
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end
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// DIVIDER
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always_ff @(posedge clk, negedge rst_n) begin
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if (~rst_n) begin
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timer_div <= '0;
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end else begin
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if (divider_up) begin
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timer_div <= dmem_wdata[SCR1_TIMER_DIVIDER_WIDTH-1:0];
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end
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end
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end
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// MTIME
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assign time_posedge = (timeclk_cnt_en & (timeclk_cnt == 0));
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always_comb begin
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mtime_new = mtime_reg;
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if (time_posedge) begin
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mtime_new = mtime_reg + 1'b1;
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end
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if (mtimelo_up) begin
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mtime_new[31:0] = dmem_wdata;
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end
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if (mtimehi_up) begin
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mtime_new[63:32] = dmem_wdata;
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end
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end
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always_ff @(posedge clk, negedge rst_n) begin
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if (~rst_n) begin
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mtime_reg <= '0;
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end else begin
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if (time_posedge | mtimelo_up | mtimehi_up) begin
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mtime_reg <= mtime_new;
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end
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end
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end
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// MTIMECMP
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always_comb begin
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mtimecmp_new = mtimecmp_reg;
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if (mtimecmplo_up) begin
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mtimecmp_new[31:0] = dmem_wdata;
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end
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if (mtimecmphi_up) begin
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mtimecmp_new[63:32] = dmem_wdata;
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end
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end
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always_ff @(posedge clk, negedge rst_n) begin
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if (~rst_n) begin
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mtimecmp_reg <= '0;
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end else begin
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if (mtimecmplo_up | mtimecmphi_up) begin
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mtimecmp_reg <= mtimecmp_new;
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end
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end
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end
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//-------------------------------------------------------------------------------
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// Interrupt pending
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//-------------------------------------------------------------------------------
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assign time_cmp_flag = (mtime_reg >= ((mtimecmplo_up | mtimecmphi_up) ? mtimecmp_new : mtimecmp_reg));
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always_ff @(posedge clk, negedge rst_n) begin
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if (~rst_n) begin
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timer_irq <= 1'b0;
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end else begin
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if (~timer_irq) begin
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timer_irq <= time_cmp_flag;
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end else begin // 1'b1
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if (mtimecmplo_up | mtimecmphi_up) begin
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timer_irq <= time_cmp_flag;
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end
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end
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end
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end
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//-------------------------------------------------------------------------------
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// Timer divider
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//-------------------------------------------------------------------------------
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assign timeclk_cnt_en = (~timer_clksrc_rtc ? 1'b1 : rtc_ext_pulse) & timer_en;
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always_ff @(negedge rst_n, posedge clk) begin
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if (~rst_n) begin
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timeclk_cnt <= '0;
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end else begin
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case (1'b1)
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divider_up : timeclk_cnt <= dmem_wdata[SCR1_TIMER_DIVIDER_WIDTH-1:0];
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time_posedge : timeclk_cnt <= timer_div;
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timeclk_cnt_en : timeclk_cnt <= timeclk_cnt - 1'b1;
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default : begin end
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endcase
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end
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end
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//-------------------------------------------------------------------------------
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// RTC synchronization
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//-------------------------------------------------------------------------------
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assign rtc_ext_pulse = rtc_sync[3] ^ rtc_sync[2];
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always_ff @(negedge rst_n, posedge rtc_clk) begin
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if (~rst_n) begin
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rtc_sync[0] <= 1'b0;
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end else begin
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if (timer_clksrc_rtc) begin
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rtc_sync[0] <= ~rtc_sync[0];
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end
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end
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end
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always_ff @(negedge rst_n, posedge clk) begin
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if (~rst_n) begin
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rtc_sync[3:1] <= '0;
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end else begin
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if (timer_clksrc_rtc) begin
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rtc_sync[3:1] <= rtc_sync[2:0];
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end
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end
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end
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//-------------------------------------------------------------------------------
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// Memory interface
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//-------------------------------------------------------------------------------
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assign dmem_req_valid = (dmem_width == SCR1_MEM_WIDTH_WORD) & (~|dmem_addr[1:0]) &
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(dmem_addr[SCR1_TIMER_ADDR_WIDTH-1:2] <= SCR1_TIMER_MTIMECMPHI[SCR1_TIMER_ADDR_WIDTH-1:2]);
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assign dmem_req_ack = 1'b1;
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always_ff @(negedge rst_n, posedge clk) begin
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if (~rst_n) begin
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dmem_resp <= SCR1_MEM_RESP_NOTRDY;
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dmem_rdata <= '0;
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end else begin
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if (dmem_req) begin
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if (dmem_req_valid) begin
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dmem_resp <= SCR1_MEM_RESP_RDY_OK;
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if (dmem_cmd == SCR1_MEM_CMD_RD) begin
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case (dmem_addr[SCR1_TIMER_ADDR_WIDTH-1:0])
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SCR1_TIMER_CONTROL : dmem_rdata <= `SCR1_DMEM_DWIDTH'({timer_clksrc_rtc, timer_en});
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SCR1_TIMER_DIVIDER : dmem_rdata <= `SCR1_DMEM_DWIDTH'(timer_div);
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SCR1_TIMER_MTIMELO : dmem_rdata <= mtime_reg[31:0];
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SCR1_TIMER_MTIMEHI : dmem_rdata <= mtime_reg[63:32];
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SCR1_TIMER_MTIMECMPLO : dmem_rdata <= mtimecmp_reg[31:0];
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SCR1_TIMER_MTIMECMPHI : dmem_rdata <= mtimecmp_reg[63:32];
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default : begin end
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endcase
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end
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end else begin
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dmem_resp <= SCR1_MEM_RESP_RDY_ER;
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end
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end else begin
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dmem_resp <= SCR1_MEM_RESP_NOTRDY;
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dmem_rdata <= '0;
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end
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end
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end
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always_comb begin
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control_up = 1'b0;
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divider_up = 1'b0;
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mtimelo_up = 1'b0;
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mtimehi_up = 1'b0;
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mtimecmplo_up = 1'b0;
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mtimecmphi_up = 1'b0;
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if (dmem_req & dmem_req_valid & (dmem_cmd == SCR1_MEM_CMD_WR)) begin
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case (dmem_addr[SCR1_TIMER_ADDR_WIDTH-1:0])
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SCR1_TIMER_CONTROL : control_up = 1'b1;
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SCR1_TIMER_DIVIDER : divider_up = 1'b1;
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SCR1_TIMER_MTIMELO : mtimelo_up = 1'b1;
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SCR1_TIMER_MTIMEHI : mtimehi_up = 1'b1;
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SCR1_TIMER_MTIMECMPLO : mtimecmplo_up = 1'b1;
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SCR1_TIMER_MTIMECMPHI : mtimecmphi_up = 1'b1;
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default : begin end
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endcase
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end
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end
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//-------------------------------------------------------------------------------
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// Timer interface
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//-------------------------------------------------------------------------------
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assign timer_val = mtime_reg;
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endmodule : scr1_timer
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