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Mikhail Yenuchenko
363
src/rtl/scr1/scr1_mem_axi.sv
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363
src/rtl/scr1/scr1_mem_axi.sv
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/// Copyright by Syntacore LLC © 2016-2020. See LICENSE for details
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/// @file <scr1_mem_axi.sv>
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/// @brief Memory AXI bridge
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///
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`include "scr1_memif.svh"
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`include "scr1_arch_description.svh"
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module scr1_mem_axi
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#(
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parameter SCR1_REQ_BUF_SIZE = 2, // Power of 2 value
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parameter SCR1_AXI_IDWIDTH = 4,
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parameter SCR1_ADDR_WIDTH = 32,
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parameter SCR1_AXI_REQ_BP = 1,
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parameter SCR1_AXI_RESP_BP = 1
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)
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(
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// Clock and Reset
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input logic clk,
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input logic rst_n,
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input logic axi_reinit,
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// Core Interface
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output logic core_idle,
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output logic core_req_ack,
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input logic core_req,
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input type_scr1_mem_cmd_e core_cmd,
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input type_scr1_mem_width_e core_width,
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input logic [SCR1_ADDR_WIDTH-1:0] core_addr,
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input logic [31:0] core_wdata,
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output logic [31:0] core_rdata,
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output type_scr1_mem_resp_e core_resp,
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// AXI
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output logic [SCR1_AXI_IDWIDTH-1:0] awid,
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output logic [SCR1_ADDR_WIDTH-1:0] awaddr,
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output logic [ 7:0] awlen,
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output logic [ 2:0] awsize,
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output logic [ 1:0] awburst,
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output logic awlock,
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output logic [ 3:0] awcache,
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output logic [ 2:0] awprot,
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output logic [ 3:0] awregion,
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output logic [ 3:0] awuser,
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output logic [ 3:0] awqos,
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output logic awvalid,
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input logic awready,
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output logic [31:0] wdata,
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output logic [3:0] wstrb,
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output logic wlast,
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output logic [3:0] wuser,
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output logic wvalid,
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input logic wready,
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input logic [SCR1_AXI_IDWIDTH-1:0] bid,
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input logic [ 1:0] bresp,
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input logic bvalid,
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input logic [ 3:0] buser,
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output logic bready,
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output logic [SCR1_AXI_IDWIDTH-1:0] arid,
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output logic [SCR1_ADDR_WIDTH-1:0] araddr,
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output logic [ 7:0] arlen,
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output logic [ 2:0] arsize,
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output logic [ 1:0] arburst,
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output logic arlock,
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output logic [ 3:0] arcache,
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output logic [ 2:0] arprot,
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output logic [ 3:0] arregion,
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output logic [ 3:0] aruser,
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output logic [ 3:0] arqos,
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output logic arvalid,
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input logic arready,
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input logic [SCR1_AXI_IDWIDTH-1:0] rid,
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input logic [31:0] rdata,
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input logic [ 1:0] rresp,
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input logic rlast,
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input logic [ 3:0] ruser,
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input logic rvalid,
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output logic rready
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);
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// Local functions
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function automatic logic [2:0] width2axsize (
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input type_scr1_mem_width_e width );
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logic [2:0] axsize;
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begin
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case (width)
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SCR1_MEM_WIDTH_BYTE : axsize = 3'b000;
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SCR1_MEM_WIDTH_HWORD: axsize = 3'b001;
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SCR1_MEM_WIDTH_WORD : axsize = 3'b010;
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default: axsize = 'x;
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endcase
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return axsize;
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end
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endfunction: width2axsize
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typedef struct packed {
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type_scr1_mem_width_e axi_width;
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logic [SCR1_ADDR_WIDTH-1:0] axi_addr;
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logic [31:0] axi_wdata;
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} type_scr1_request_s;
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typedef struct packed {
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logic req_write;
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logic req_addr;
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logic req_data;
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logic req_resp;
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} type_scr1_req_status_s;
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type_scr1_request_s [SCR1_REQ_BUF_SIZE-1:0] req_fifo;
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type_scr1_req_status_s [SCR1_REQ_BUF_SIZE-1:0] req_status;
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type_scr1_req_status_s [SCR1_REQ_BUF_SIZE-1:0] req_status_new;
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logic [SCR1_REQ_BUF_SIZE-1:0] req_status_en;
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logic [$clog2(SCR1_REQ_BUF_SIZE)-1:0] req_aval_ptr;
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logic [$clog2(SCR1_REQ_BUF_SIZE)-1:0] req_proc_ptr;
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logic [$clog2(SCR1_REQ_BUF_SIZE)-1:0] req_done_ptr;
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logic rresp_err;
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logic [31:0] rcvd_rdata;
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type_scr1_mem_resp_e rcvd_resp;
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logic force_read;
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logic force_write;
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assign core_req_ack = ~axi_reinit &
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~req_status[req_aval_ptr].req_resp &
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core_resp!=SCR1_MEM_RESP_RDY_ER;
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assign rready = ~req_status[req_done_ptr].req_write;
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assign bready = req_status[req_done_ptr].req_write;
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assign force_read = bit'(SCR1_AXI_REQ_BP) & core_req & core_req_ack & req_aval_ptr==req_proc_ptr & core_cmd==SCR1_MEM_CMD_RD;
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assign force_write = bit'(SCR1_AXI_REQ_BP) & core_req & core_req_ack & req_aval_ptr==req_proc_ptr & core_cmd==SCR1_MEM_CMD_WR;
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always_comb begin: idle_status
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core_idle = 1'b1;
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for (int unsigned i=0; i<SCR1_REQ_BUF_SIZE; ++i) begin
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core_idle &= req_status[i].req_resp==1'b0;
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end
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end
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always_ff @(posedge clk) begin
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if (core_req & core_req_ack) begin
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req_fifo[req_aval_ptr].axi_width <= core_width;
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req_fifo[req_aval_ptr].axi_addr <= core_addr;
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req_fifo[req_aval_ptr].axi_wdata <= core_wdata;
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end
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end
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// Request Status Queue
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// It is used for holding control info of processing requests
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// Combinational logic of Request Status Queue
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always_comb begin
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// Default
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req_status_en = '0; // No update
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req_status_new = req_status; // Hold request info
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// Update status on new core request
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if( core_req & core_req_ack ) begin
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req_status_en[req_aval_ptr] = 1'd1;
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req_status_new[req_aval_ptr].req_resp = 1'd1;
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req_status_new[req_aval_ptr].req_write = core_cmd == SCR1_MEM_CMD_WR;
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req_status_new[req_aval_ptr].req_addr = ~( (force_read & arready) |
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(force_write & awready) );
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req_status_new[req_aval_ptr].req_data = ~( (force_write & wready & awlen == 8'd0) |
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(~force_write & core_cmd == SCR1_MEM_CMD_RD) );
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end
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// Update status on AXI address phase
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if ( (awvalid & awready) | (arvalid & arready) ) begin
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req_status_en[req_proc_ptr] = 1'd1;
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req_status_new[req_proc_ptr].req_addr = 1'd0;
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end
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// Update status on AXI data phase
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if ( wvalid & wready & wlast ) begin
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req_status_en[req_proc_ptr] = 1'd1;
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req_status_new[req_proc_ptr].req_data = 1'd0;
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end
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// Update status when AXI finish transaction
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if ( (bvalid & bready) | (rvalid & rready & rlast) ) begin
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req_status_en[req_done_ptr] = 1'd1;
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req_status_new[req_done_ptr].req_resp = 1'd0;
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end
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end
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// Request Status Queue register
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always_ff @(negedge rst_n, posedge clk) begin
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if (~rst_n) begin
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req_status <= '0;
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end else begin
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for (int unsigned i = 0; i < SCR1_REQ_BUF_SIZE; ++i) begin
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if ( req_status_en[i] ) begin
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req_status[i] <= req_status_new[i];
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end
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end
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end
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end
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always_ff @(negedge rst_n, posedge clk) begin
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if (~rst_n) req_aval_ptr <= '0;
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else if (core_req & core_req_ack) req_aval_ptr <= req_aval_ptr + 1'b1;
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end
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always_ff @(negedge rst_n, posedge clk) begin
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if (~rst_n) begin
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req_proc_ptr <= '0;
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end else begin
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if (( awvalid & awready & wvalid & wready & wlast) |
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(~force_write & ~req_status[req_proc_ptr].req_data & awvalid & awready ) |
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(~force_write & ~req_status[req_proc_ptr].req_addr & wvalid & wready & wlast) |
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( ~req_status[req_proc_ptr].req_data & arvalid & arready ) ) begin
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req_proc_ptr <= req_proc_ptr + 1'b1;
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end
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end
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end
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always_ff @(negedge rst_n, posedge clk) begin
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if (~rst_n) begin
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req_done_ptr <= '0;
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end else begin
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if ((bvalid & bready | rvalid & rready & rlast) & req_status[req_done_ptr].req_resp) begin
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req_done_ptr <= req_done_ptr + 1'b1;
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end
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end
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end
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assign arvalid = req_status[req_proc_ptr].req_addr & ~req_status[req_proc_ptr].req_write | force_read;
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assign awvalid = req_status[req_proc_ptr].req_addr & req_status[req_proc_ptr].req_write | force_write;
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assign wvalid = req_status[req_proc_ptr].req_data & req_status[req_proc_ptr].req_write | force_write;
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assign araddr = (~force_read )? req_fifo[req_proc_ptr].axi_addr : core_addr;
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assign awaddr = (~force_write)? req_fifo[req_proc_ptr].axi_addr : core_addr;
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always_comb begin
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if (bvalid & bready & req_status[req_done_ptr].req_resp) begin
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rcvd_resp = (bresp==2'b00)? SCR1_MEM_RESP_RDY_OK :
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SCR1_MEM_RESP_RDY_ER;
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end else begin
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if (rvalid & rready & rlast & req_status[req_done_ptr].req_resp) begin
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rcvd_resp = (rresp==2'b00)? SCR1_MEM_RESP_RDY_OK :
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SCR1_MEM_RESP_RDY_ER;
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end else begin
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rcvd_resp = SCR1_MEM_RESP_NOTRDY;
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end
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end
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end
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// Write data signals adaptation
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always_comb begin
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if (force_write)
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case (core_width)
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SCR1_MEM_WIDTH_BYTE : wstrb = 4'h1 << core_addr[1:0];
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SCR1_MEM_WIDTH_HWORD: wstrb = 4'h3 << core_addr[1:0];
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SCR1_MEM_WIDTH_WORD : wstrb = 4'hf << core_addr[1:0];
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default: wstrb = 'x;
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endcase
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else
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case (req_fifo[req_proc_ptr].axi_width)
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SCR1_MEM_WIDTH_BYTE : wstrb = 4'h1 << req_fifo[req_proc_ptr].axi_addr[1:0];
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SCR1_MEM_WIDTH_HWORD: wstrb = 4'h3 << req_fifo[req_proc_ptr].axi_addr[1:0];
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SCR1_MEM_WIDTH_WORD : wstrb = 4'hf << req_fifo[req_proc_ptr].axi_addr[1:0];
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default: wstrb = 'x;
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endcase
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end
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assign wdata = (force_write)? core_wdata << (8* core_addr[1:0]) :
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req_fifo[req_proc_ptr].axi_wdata << (8* req_fifo[req_proc_ptr].axi_addr[1:0]);
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// Read data adaptation
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always_comb begin
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case (req_fifo[req_done_ptr].axi_width)
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SCR1_MEM_WIDTH_BYTE : rcvd_rdata = rdata >> (8*req_fifo[req_done_ptr].axi_addr[1:0]);
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SCR1_MEM_WIDTH_HWORD: rcvd_rdata = rdata >> (8*req_fifo[req_done_ptr].axi_addr[1:0]);
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SCR1_MEM_WIDTH_WORD : rcvd_rdata = rdata >> (8*req_fifo[req_done_ptr].axi_addr[1:0]);
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default: rcvd_rdata = 'x;
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endcase
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end
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generate
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if (SCR1_AXI_RESP_BP == 1) begin : axi_resp_bp
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assign core_rdata = (rvalid & rready & rlast) ? rcvd_rdata : '0;
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assign core_resp = (axi_reinit) ? SCR1_MEM_RESP_NOTRDY : rcvd_resp;
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end else begin : axi_resp_no_bp
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always_ff @(negedge rst_n, posedge clk) begin
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if (~rst_n) core_resp <= SCR1_MEM_RESP_NOTRDY;
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else core_resp <= (axi_reinit) ? SCR1_MEM_RESP_NOTRDY : rcvd_resp;
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end
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always_ff @(posedge clk) begin
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if (rvalid & rready & rlast) core_rdata <= rcvd_rdata;
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end
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end
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endgenerate
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// AXI interface assignments
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assign awid = SCR1_AXI_IDWIDTH'(1);
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assign awlen = 8'd0;
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assign awsize = (force_write) ? width2axsize(core_width) : width2axsize(req_fifo[req_proc_ptr].axi_width);
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assign awburst = 2'd1;
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assign awcache = 4'd2;
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assign awlock = '0;
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assign awprot = '0;
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assign awregion = '0;
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assign awuser = '0;
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assign awqos = '0;
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assign arid = SCR1_AXI_IDWIDTH'(0);
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assign arlen = 8'd0;
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assign arsize = (force_read) ? width2axsize(core_width) : width2axsize(req_fifo[req_proc_ptr].axi_width);
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assign arburst = 2'd1;
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assign arcache = 4'd2;
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assign arprot = '0;
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assign arregion = '0;
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assign arlock = '0;
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assign arqos = '0;
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assign aruser = '0;
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assign wlast = 1'd1;
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assign wuser = '0;
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`ifdef SCR1_TRGT_SIMULATION
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//-------------------------------------------------------------------------------
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// Assertion
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//-------------------------------------------------------------------------------
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// X checks
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SCR1_SVA_AXI_X_CHECK0 : assert property (@(negedge clk) disable iff (~rst_n) !$isunknown({core_req, awready, wready, bvalid, arready, rvalid}) )
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else $error("AXI bridge: X state on input");
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SCR1_SVA_AXI_X_CHECK1 : assert property (@(negedge clk) disable iff (~rst_n) core_req |->
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!$isunknown({core_cmd, core_width, core_addr}) )
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else $error("AXI bridge: X state on input");
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SCR1_SVA_AXI_X_CHECK2 : assert property (@(negedge clk) disable iff (~rst_n) bvalid |->
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!$isunknown({bid, bresp}) )
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else $error("AXI bridge: X state on input");
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SCR1_SVA_AXI_X_CHECK3 : assert property (@(negedge clk) disable iff (~rst_n) rvalid |->
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!$isunknown({rid, rresp}) )
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else $error("AXI bridge: X state on input");
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`endif // SCR1_TRGT_SIMULATION
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endmodule : scr1_mem_axi
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