diff --git a/scripts/scripts_syn/RUN_SYN.tcl b/scripts/scripts_syn/RUN_SYN.tcl
index f2eaebf..524a4b9 100644
--- a/scripts/scripts_syn/RUN_SYN.tcl
+++ b/scripts/scripts_syn/RUN_SYN.tcl
@@ -9,11 +9,13 @@
 ### - cd to the main folder with the scripts, src, reports etc. (BE_ASIC_DESIGN_CADENCE_SCRIPTS folder) and then cd to the ./WORK_TMP_FOLDER
 ### - run synthesis with RTL Compiler by typing in the same terminal "RTL_Compiler ../scripts/scripts_syn/RUN_SYN.tcl"
 
+
+
 ### ================= USER SETTINGS =================
 set RTL_TOP_NAME "scr1_top_ahb";                                         # RTL top module name
 set RTL_PATH "../src/rtl";                                       # RTL path to the source files
 
-set RTL_FILELIST_NAME "filelist.v";                             # RTL path to the filelist for synthesis
+set RTL_FILELIST_NAME "filelist.v";                            # RTL path to the filelist for synthesis
 
 set SYN_SDC_TOP_NAME "${RTL_TOP_NAME}.sdc";                       # SDC top file name
 set SYN_SDC_PATH "../src/sdc";                                   # SDC path to the sources
@@ -24,6 +26,12 @@ set SYN_REPORTS_FOLDER "../reports/reports_syn";                 # Reports folde
 set SYN_RESULTS_FOLDER "../results/results_syn";                 # Results folder
 ### ================= END of USER SETTINGS ==========
 
+### ============== PROC to run synthesis ============
+### Set TRUE to enable technological mapping and results export; otherwise only elaboration is active
+#set MAPPING  "FALSE";
+set MAPPING  "TRUE";
+### ========== end of PROC to run synthesis =========
+
 
 
 ### ================= SYNTHESIS =================
@@ -33,26 +41,28 @@ include ${SYN_CORNER}
 # Read in Verilog HDL filelist for synthesis
 read_hdl -sv ${RTL_PATH}/${RTL_FILELIST_NAME}
 
-# Synthesize (elabirate, no mapping)
+# Synthesize (elaborate, no mapping)
 elaborate ${RTL_TOP_NAME}
 
-# Rear SDC constraints
-read_sdc ${SYN_SDC_PATH}/${SYN_SDC_TOP_NAME}
+if {$MAPPING eq "TRUE"} {
+   # Rear SDC constraints
+   read_sdc ${SYN_SDC_PATH}/${SYN_SDC_TOP_NAME}
 
-# Synthesize (technology mapped)
-synthesize -to_mapped
-synthesize -incremental
+   # Synthesize (technology mapped)
+   synthesize -to_mapped
+   synthesize -incremental
 
-# Generate area and timing reports
-report timing                > ${SYN_REPORTS_FOLDER}/${RTL_TOP_NAME}_syn_timing_report.rpt
-report area                  > ${SYN_REPORTS_FOLDER}/${RTL_TOP_NAME}_syn_area_report.rpt
-report_timing -lint -verbose > ${SYN_REPORTS_FOLDER}/${RTL_TOP_NAME}_syn_timing_problems.rpt
+   # Generate area and timing reports
+   report timing                > ${SYN_REPORTS_FOLDER}/${RTL_TOP_NAME}_syn_timing_report.rpt
+   report area                  > ${SYN_REPORTS_FOLDER}/${RTL_TOP_NAME}_syn_area_report.rpt
+   report_timing -lint -verbose > ${SYN_REPORTS_FOLDER}/${RTL_TOP_NAME}_syn_timing_problems.rpt
 
-# Export synthesized and mapped Verilog netlist - result of the synthesis
-write_hdl -mapped > ${SYN_RESULTS_FOLDER}/${RTL_TOP_NAME}_syn_netlist.v
+   # Export synthesized and mapped Verilog netlist - result of the synthesis
+   write_hdl -mapped > ${SYN_RESULTS_FOLDER}/${RTL_TOP_NAME}_syn_netlist.v
 
-# Export SDC file for the next PaR stages
-write_sdc > ${SYN_RESULTS_FOLDER}/${RTL_TOP_NAME}_syn.sdc
+   # Export SDC file for the next PaR stages
+   write_sdc > ${SYN_RESULTS_FOLDER}/${RTL_TOP_NAME}_syn.sdc
+}
 
 # Open RTL Compiler GUI
 gui_show