Add scripts
This commit is contained in:
Mikhail Yenuchenko
197
scripts/scripts_PaR/FLOW_PAR.tcl
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197
scripts/scripts_PaR/FLOW_PAR.tcl
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### This is a sample RUN TCL file describing each step of the PaR.
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### We are using RTL Compiler (synthesis) and Encounter (PaR) from the the Cadence Inc.
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### The current technology is XFAB 180nm
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### ================= INITIAL SETTINGS =================
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if {$PaR_INIT eq "TRUE"} {
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set init_pwr_net VDD; # Define supply VDD net
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set init_gnd_net VSS; # Define supply VSS net
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set init_lef_file ${PAR_INIT_LEF_FILESET}; # Physical libraries - LEF fileset from XFAB 180nm
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set init_design_settop 0;
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set init_verilog ${NETLIST_PATH}/${NETLIST_TOP_NAME}; # SYN netlist file
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set init_mmmc_file ${PAR_MMMC_FILE}; # Techmological file for multi-mode multi-corner PaR
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set init_io_file ${PAR_NETLIST_TOP_PORT_FILE}; # File with location of the TOP level ports on the floorplan
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init_design
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}
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### ================= END of INITIAL SETTINGS =========
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### ================= FLOORPLANNING ====================
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if {$PaR_FP eq "TRUE"} {
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floorPlan -site core_hd -s "${FLOORPLAN_DIMENSIONS} ${FLOORPLAN_MARGINS}";
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floorPlan -coreMarginsBy die -site core_hd -s "${FLOORPLAN_DIMENSIONS} ${FLOORPLAN_MARGINS}";
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}
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### ================= END of FLOORPLANNING ============
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### ================= POWER DELIVERY SYSTEM ====================
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if {$PaR_PWR eq "TRUE"} {
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#GLOBAL CONNECTIONS
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clearGlobalNets
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globalNetConnect VDD -type pgpin -pin vdd -inst * -module {}
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globalNetConnect VSS -type pgpin -pin gnd -inst * -module {}
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globalNetConnect VDD -type tiehi -pin vdd -inst * -module {}
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globalNetConnect VSS -type tielo -pin gnd -inst * -module {}
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# POWER RING
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addRing -skip_via_on_wire_shape Noshape -skip_via_on_pin Standardcell -stacked_via_top_layer METTPL -type core_rings -jog_distance 3.15 -threshold 3.15 -nets {VDD VSS} -follow core -stacked_via_bottom_layer MET1 -layer {bottom METTP top METTP right METTPL left METTPL} -width 10 -spacing 5 -offset 3.15
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# POWER STRAPS
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addStripe -skip_via_on_wire_shape Noshape -block_ring_top_layer_limit MET3 -max_same_layer_jog_length 6 -padcore_ring_bottom_layer_limit MET1 -set_to_set_distance 85 -skip_via_on_pin Standardcell -stacked_via_top_layer METTPL -padcore_ring_top_layer_limit MET3 -spacing 5 -merge_stripes_value 3.15 -layer METTPL -block_ring_bottom_layer_limit MET1 -width 10 -nets {VSS VDD} -stacked_via_bottom_layer MET1
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# REMOVE UNUNSED
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#selectWire 39.6900 6.5100 59.6900 5073.6900 2 VSS ; #TODO
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#deleteSelectedFromFPlan; #TODO
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#selectWire 64.6900 22.1100 84.6900 5058.0900 2 VDD ; #TODO
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#deleteSelectedFromFPlan; #TODO
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# MAKE A PG CONNECTIONS
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sroute -connect { blockPin padPin padRing corePin floatingStripe } -layerChangeRange { MET1 METTPL } -blockPinTarget { nearestTarget } -padPinPortConnect { allPort oneGeom } -padPinTarget { nearestTarget } -corePinTarget { firstAfterRowEnd } -floatingStripeTarget { blockring padring ring stripe ringpin blockpin followpin } -allowJogging 1 -crossoverViaLayerRange { MET1 METTPL } -allowLayerChange 1 -nets { VDD VSS } -blockPin useLef -targetViaLayerRange { MET1 METTPL }
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editPowerVia -skip_via_on_pin Standardcell -bottom_layer MET1 -add_vias 1 -top_layer METTPL
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# AFTER-STAGE STA
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timeDesign -prePlace -idealClock -pathReports -drvReports -slackReports -numPaths 50 -prefix ${NETLIST_TOP_NAME}_FP_PG_SETUP -outDir ${PAR_REPORTS_FOLDER}; # SETUP STA
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}
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### ================= END of POWER DELIVERY SYSTEM ============
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### ================= PLACEMENT ====================
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if {$PaR_PLACE eq "TRUE"} {
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# GENERAL SETTINGS - CPU num etc.
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setMultiCpuUsage -localCpu 8 -cpuPerRemoteHost 1 -remoteHost 0 -keepLicense true
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setDistributeHost -local
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setPlaceMode -fp false
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### PLACE
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placeDesign -inPlaceOpt
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# POST-PLACE STA
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timeDesign -preCTS -idealClock -pathReports -drvReports -slackReports -numPaths 50 -prefix ${NETLIST_TOP_NAME}_PLACE_SETUP -outDir ${PAR_REPORTS_FOLDER}; # SETUP STA
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timeDesign -preCTS -hold -idealClock -pathReports -slackReports -numPaths 50 -prefix ${NETLIST_TOP_NAME}_PLACE_HOLD -outDir ${PAR_REPORTS_FOLDER}; # HOLD STA
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# OPTIMIZATION
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setOptMode -fixCap true -fixTran true -fixFanoutLoad true
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optDesign -preCTS
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# POST-OPTIMIZATION STA
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timeDesign -preCTS -hold -idealClock -pathReports -slackReports -numPaths 50 -prefix ${NETLIST_TOP_NAME}_PLACE_HOLD_OPT -outDir ${PAR_REPORTS_FOLDER}; # HOLD STA
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}
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### ================= END of PLACEMENT =============
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### ================= CTS ====================
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if {$PaR_CTS eq "TRUE"} {
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# BUFFER SORTING
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createClockTreeSpec -bufferList {BUHDX0 BUHDX1 BUHDX12 BUHDX2 BUHDX3 BUHDX4 BUHDX6 BUHDX8 DLY1HDX0 DLY1HDX1 DLY2HDX0 DLY2HDX1 DLY4HDX0 DLY4HDX1 DLY8HDX0 DLY8HDX1 INHDX0 INHDX1 INHDX12 INHDX2 INHDX3 INHDX4 INHDX6 INHDX8 STEHDX0 STEHDX1 STEHDX2 STEHDX4} -file Clock.ctstch
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# CTS
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setCTSMode -engine ck
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clockDesign -specFile Clock.ctstch -outDir ${PAR_REPORTS_FOLDER} -fixedInstBeforeCTS
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# POST-CTS STA
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timeDesign -postCTS -pathReports -drvReports -slackReports -numPaths 50 -prefix ${NETLIST_TOP_NAME}_CTS_SETUP -outDir ${PAR_REPORTS_FOLDER}; # SETUP STA
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timeDesign -postCTS -hold -pathReports -slackReports -numPaths 50 -prefix ${NETLIST_TOP_NAME}_CTS_HOLD -outDir ${PAR_REPORTS_FOLDER}; # HOLD STA
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### OPTIMIZATION
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setOptMode -fixCap true -fixTran true -fixFanoutLoad true
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optDesign -postCTS
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optDesign -postCTS -hold
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# POST-OPT STA
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timeDesign -postCTS -hold -pathReports -slackReports -numPaths 50 -prefix ${NETLIST_TOP_NAME}_CTS_HOLD_OPT -outDir ${PAR_REPORTS_FOLDER}; # HOLD STA
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# INCREMENTAL OPT
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optDesign -postCTS -hold -incr
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# POST-INCR STA
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timeDesign -postCTS -hold -pathReports -slackReports -numPaths 50 -prefix ${NETLIST_TOP_NAME}_CTS_HOLD_INCR_OPT -outDir ${PAR_REPORTS_FOLDER}; # HOLD STA
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}
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### ================= END of CTS =============
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### ================= ROUTE ====================
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if {$PaR_ROUTE eq "TRUE"} {
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# GENERAL SETTINGS
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setNanoRouteMode -quiet -timingEngine {}
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setNanoRouteMode -quiet -routeWithSiPostRouteFix 0
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setNanoRouteMode -quiet -routeTopRoutingLayer default
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setNanoRouteMode -quiet -routeBottomRoutingLayer default
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setNanoRouteMode -quiet -drouteEndIteration default
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setNanoRouteMode -quiet -routeWithTimingDriven false
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setNanoRouteMode -quiet -routeWithSiDriven false
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# ANTENNA VILOATION FIX - BRIDGE
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setNanoRouteMode -quiet -drouteFixAntenna true
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# ANTENNA VILOATION FIX - DIODES
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setNanoRouteMode -quiet -routeInsertAntennaDiode true
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# ROUTE
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routeDesign -globalDetail
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# POST-ROUTE STA
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setAnalysisMode -analysisType onChipVariation -skew true -clockPropagation sdcControl
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timeDesign -postRoute -pathReports -drvReports -slackReports -numPaths 50 -prefix ${NETLIST_TOP_NAME}_ROUTE_SETUP -outDir ${PAR_REPORTS_FOLDER}; # SETUP STA
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timeDesign -postRoute -hold -pathReports -slackReports -numPaths 50 -prefix ${NETLIST_TOP_NAME}_ROUTE_HOLD -outDir ${PAR_REPORTS_FOLDER}; # HOLD STA
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# OPTIMIZATION
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setOptMode -fixCap true -fixTran true -fixFanoutLoad true
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optDesign -postRoute
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optDesign -postRoute -hold
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# POST-OPT STA
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timeDesign -postRoute -hold -pathReports -slackReports -numPaths 50 -prefix ${NETLIST_TOP_NAME}_ROUTE_HOLD_OPT -outDir ${PAR_REPORTS_FOLDER}; # HOLD STA
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# INCREMENTAL OPT
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optDesign -postRoute -incr
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optDesign -postRoute -hold -incr
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# POST-INCR STA
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timeDesign -postRoute -hold -pathReports -slackReports -numPaths 50 -prefix ${NETLIST_TOP_NAME}_ROUTE_HOLD_INCR_OPT -outDir ${PAR_REPORTS_FOLDER}; # HOLD STA
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}
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### ================= END of ROUTE ====================
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### ================= FINALIZATION ====================
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if {$PaR_FINAL eq "TRUE"} {
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# FILLER CELLS
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getFillerMode -quiet
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addFiller -cell FEED7HD FEED5HD FEED3HD FEED2HD FEED25HD FEED1HD FEED15HD FEED10HD -prefix FILLER
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# CHECK SIMPLE DRC
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setVerifyGeometryMode -area { 0 0 0 0 } -minWidth true -minSpacing true -minArea true -sameNet true -short true -overlap true -offRGrid false -offMGrid true -mergedMGridCheck true -minHole true -implantCheck true -minimumCut true -minStep true -viaEnclosure true -antenna false -insuffMetalOverlap true -pinInBlkg true -diffCellViol false -sameCellViol true -padFillerCellsOverlap false -routingBlkgPinOverlap false -routingCellBlkgOverlap false -regRoutingOnly false -stackedViasOnRegNet false -wireExt true -useNonDefaultSpacing false -maxWidth true -maxNonPrefLength -1 -error 1000
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verifyGeometry -report ${PAR_REPORTS_FOLDER}/${NETLIST_TOP_NAME}_GEOMETRY.rpt
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setVerifyGeometryMode -area { 0 0 0 0 }
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verify_drc -report ${PAR_REPORTS_FOLDER}/${NETLIST_TOP_NAME}_DRC.rpt -limit 1000
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verifyConnectivity -type all -error 1000 -warning 50 -report ${PAR_REPORTS_FOLDER}/${NETLIST_TOP_NAME}_CONNECTIVITY.rpt
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# EXTRACT RC
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setExtractRCMode -engine postRoute -effortLevel signoff
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extractRC
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}
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### ================= END of FINALIZATION ====================
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### ================= OUTPUT ====================
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if {$PaR_OUT eq "TRUE"} {
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# STA
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timeDesign -signoff -pathReports -drvReports -slackReports -numPaths 50 -prefix ${NETLIST_TOP_NAME}_SIGNOFF_SETUP -outDir ${PAR_REPORTS_FOLDER}; # "-signoff" SETUP STA
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timeDesign -signoff -hold -pathReports -slackReports -numPaths 50 -prefix ${NETLIST_TOP_NAME}_SIGNOFF_HOLD -outDir ${PAR_REPORTS_FOLDER}; # "-signoff" HOLD STA
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all_hold_analysis_views
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all_setup_analysis_views
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# Drop file extenstion
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set FILENAME [string trimright ${NETLIST_TOP_NAME} .v]
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# Create folder
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if {![file exists ${PAR_RESULTS_FOLDER}]} {
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file mkdir ${PAR_RESULTS_FOLDER}
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}
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# EXPORT RESULTS of the PaR stage
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write_sdf -view TYPview ${PAR_RESULTS_FOLDER}/${FILENAME}.sdf
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saveNetlist ${PAR_RESULTS_FOLDER}/${FILENAME}.v -includePhysicalCell {FEED7HD FEED10HD FEED15HD FEED1HD FEED25HD FEED2HD FEED3HD FEED5HD}
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defOut -floorplan -netlist -routing ${PAR_RESULTS_FOLDER}/${FILENAME}.def
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}
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### ================= END of OUTPUT ====================
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52
scripts/scripts_PaR/RUN_PAR.tcl
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52
scripts/scripts_PaR/RUN_PAR.tcl
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### This is a sample RUN TCL file to control the stages of the digital ASIC BE flow
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### We are using RTL Compiler (synthesis) and Encounter (PaR) from the the Cadence Inc.
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### The current technology is XFAB 180nm
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### For current flow the following assumptions are expected:
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### - set all USER settings;
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### - check that netlist and exported synthesis SDC are exisits with consistent names;
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### - open the terminal
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### - cd to the main folder with the scripts, src, reports etc. (BE_ASIC_DESIGN_CADENCE_SCRIPTS folder) and then cd to the ./WORK_TMP_FOLDER
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### - run Place-and-Route with Encounter by typing in the same terminal "Encounter ../scripts/scripts_PaR/RUN_PAR.tcl"
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### ================= USER SETTINGS =================
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set NETLIST_TOP_NAME "PWM_syn_netlist.v"; # RTL top module name
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set NETLIST_PATH "../results/results_syn"; # RTL path to the source files
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set PAR_SDC_TOP_NAME "PWM_syn.sdc"; # SDC top file name
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set PAR_SDC_PATH "../results/results_syn"; # SDC path to the sources
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set PAR_MMMC_FILE "../scripts/scripts_aux/XFAB180_MMMC.tcl"; # Multi-mode multi-corner file
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set PAR_NETLIST_TOP_PORT_FILE "../scripts/scripts_aux/PaR_NETLIST_TOP_PORT_FILE"; # Synthesis corner (typ by default)
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set PAR_INIT_LEF_FILESET "/Cadence/Libs/X_FAB/XKIT/xt018/cadence/v7_0/techLEF/v7_0_1_1/xt018_xx43_MET4_METMID_METTHK.lef \
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/Cadence/Libs/X_FAB/XKIT/xt018/diglibs/D_CELLS_HD/v4_0/LEF/v4_0_0/xt018_D_CELLS_HD.lef \
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/Cadence/Libs/X_FAB/XKIT/xt018/diglibs/D_CELLS_HD/v4_0/LEF/v4_0_0/xt018_xx43_MET4_METMID_METTHK_D_CELLS_HD_mprobe.lef";
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set PAR_REPORTS_FOLDER "../reports/reports_PaR"; # Reports folder
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set PAR_RESULTS_FOLDER "../results/results_PaR"; # Results folder
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set FLOORPLAN_DIMENSIONS {200 200}; # FP chip area
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set FLOORPLAN_MARGINS {50 50 50 50}; #FP chip margins
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### ================= END of USER SETTINGS =============
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### ================== PROC to run PaR =================
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### Set TRUE/FALSE and re-source RUN_PAR.tcl again in the interactive Encounter TCL shell
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set PaR_INIT "TRUE";
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set PaR_FP "TRUE";
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set PaR_PWR "TRUE";
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set PaR_PLACE "TRUE";
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set PaR_CTS "TRUE";
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set PaR_ROUTE "TRUE";
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set PaR_FINAL "TRUE";
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set PaR_OUT "TRUE";
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### ============== END of PROC to run PaR ==============
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source ../scripts/scripts_PaR/FLOW_PAR.tcl; # Source PaR steps from the user TCL file
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# Open Encounter GUI
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win
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60
scripts/scripts_syn/RUN_SYN.tcl
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60
scripts/scripts_syn/RUN_SYN.tcl
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### This is a sample RUN TCL file to control the stages of the digital ASIC BE flow
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### We are using RTL Compiler (synthesis) and Encounter (PaR) from the the Cadence Inc.
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### The current technology is XFAB 180nm
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### For current flow the following assumptions are expected:
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### - set all USER settings;
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### - create requred SDC file with the same name as your RTL top (e.g. RTL_TOP_MODULE.sdc)
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### - open the terminal
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### - cd to the main folder with the scripts, src, reports etc. (BE_ASIC_DESIGN_CADENCE_SCRIPTS folder) and then cd to the ./WORK_TMP_FOLDER
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### - run synthesis with RTL Compiler by typing in the same terminal "RTL_Compiler ../scripts/scripts_syn/RUN_SYN.tcl"
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### ================= USER SETTINGS =================
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set RTL_TOP_NAME "scr1_top_ahb"; # RTL top module name
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set RTL_PATH "../src/rtl"; # RTL path to the source files
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set RTL_FILELIST_NAME "filelist.v"; # RTL path to the filelist for synthesis
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set SYN_SDC_TOP_NAME "${RTL_TOP_NAME}.sdc"; # SDC top file name
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set SYN_SDC_PATH "../src/sdc"; # SDC path to the sources
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set SYN_CORNER "../scripts/scripts_aux/XFAB180_typ.tcl"; # Synthesis corner (typ by default)
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set SYN_REPORTS_FOLDER "../reports/reports_syn"; # Reports folder
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set SYN_RESULTS_FOLDER "../results/results_syn"; # Results folder
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### ================= END of USER SETTINGS ==========
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### ================= SYNTHESIS =================
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# Source desired corner technology file for synthesis
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include ${SYN_CORNER}
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# Read in Verilog HDL filelist for synthesis
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read_hdl -sv ${RTL_PATH}/${RTL_FILELIST_NAME}
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# Synthesize (elabirate, no mapping)
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elaborate ${RTL_TOP_NAME}
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# Rear SDC constraints
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read_sdc ${SYN_SDC_PATH}/${SYN_SDC_TOP_NAME}
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# Synthesize (technology mapped)
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synthesize -to_mapped
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synthesize -incremental
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# Generate area and timing reports
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report timing > ${SYN_REPORTS_FOLDER}/${RTL_TOP_NAME}_syn_timing_report.rpt
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report area > ${SYN_REPORTS_FOLDER}/${RTL_TOP_NAME}_syn_area_report.rpt
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report_timing -lint -verbose > ${SYN_REPORTS_FOLDER}/${RTL_TOP_NAME}_syn_timing_problems.rpt
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# Export synthesized and mapped Verilog netlist - result of the synthesis
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write_hdl -mapped > ${SYN_RESULTS_FOLDER}/${RTL_TOP_NAME}_syn_netlist.v
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# Export SDC file for the next PaR stages
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write_sdc > ${SYN_RESULTS_FOLDER}/${RTL_TOP_NAME}_syn.sdc
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# Open RTL Compiler GUI
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gui_show
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### ================= END of SYNTHESIS ==========
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