Folder rename
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Mikhail Yenuchenko
701
src_ref/top/scr1_top_axi.sv
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701
src_ref/top/scr1_top_axi.sv
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/// Copyright by Syntacore LLC © 2016-2020. See LICENSE for details
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/// @file <scr1_top_axi.sv>
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/// @brief SCR1 AXI top
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///
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`include "scr1_arch_description.svh"
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`include "scr1_memif.svh"
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`ifdef SCR1_IPIC_EN
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`include "scr1_ipic.svh"
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`endif // SCR1_IPIC_EN
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`ifdef SCR1_TCM_EN
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`define SCR1_IMEM_ROUTER_EN
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`endif // SCR1_TCM_EN
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module scr1_top_axi (
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// Control
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input logic pwrup_rst_n, // Power-Up Reset
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input logic rst_n, // Regular Reset signal
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input logic cpu_rst_n, // CPU Reset (Core Reset)
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input logic test_mode, // Test mode
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input logic test_rst_n, // Test mode's reset
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input logic clk, // System clock
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input logic rtc_clk, // Real-time clock
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`ifdef SCR1_DBG_EN
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output logic sys_rst_n_o, // External System Reset output
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// (for the processor cluster's components or
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// external SOC (could be useful in small
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// SCR-core-centric SOCs))
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output logic sys_rdc_qlfy_o, // System-to-External SOC Reset Domain Crossing Qualifier
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`endif // SCR1_DBG_EN
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// Fuses
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input logic [`SCR1_XLEN-1:0] fuse_mhartid, // Hart ID
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`ifdef SCR1_DBG_EN
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input logic [31:0] fuse_idcode, // TAPC IDCODE
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`endif // SCR1_DBG_EN
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// IRQ
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`ifdef SCR1_IPIC_EN
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input logic [SCR1_IRQ_LINES_NUM-1:0] irq_lines, // IRQ lines to IPIC
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`else // SCR1_IPIC_EN
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input logic ext_irq, // External IRQ input
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`endif // SCR1_IPIC_EN
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input logic soft_irq, // Software IRQ input
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`ifdef SCR1_DBG_EN
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// -- JTAG I/F
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input logic trst_n,
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input logic tck,
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input logic tms,
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input logic tdi,
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output logic tdo,
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output logic tdo_en,
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`endif // SCR1_DBG_EN
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// Instruction Memory Interface
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output logic [3:0] io_axi_imem_awid,
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output logic [31:0] io_axi_imem_awaddr,
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output logic [7:0] io_axi_imem_awlen,
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output logic [2:0] io_axi_imem_awsize,
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output logic [1:0] io_axi_imem_awburst,
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output logic io_axi_imem_awlock,
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output logic [3:0] io_axi_imem_awcache,
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output logic [2:0] io_axi_imem_awprot,
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output logic [3:0] io_axi_imem_awregion,
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output logic [3:0] io_axi_imem_awuser,
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output logic [3:0] io_axi_imem_awqos,
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output logic io_axi_imem_awvalid,
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input logic io_axi_imem_awready,
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output logic [31:0] io_axi_imem_wdata,
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output logic [3:0] io_axi_imem_wstrb,
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output logic io_axi_imem_wlast,
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output logic [3:0] io_axi_imem_wuser,
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output logic io_axi_imem_wvalid,
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input logic io_axi_imem_wready,
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input logic [3:0] io_axi_imem_bid,
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input logic [1:0] io_axi_imem_bresp,
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input logic io_axi_imem_bvalid,
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input logic [3:0] io_axi_imem_buser,
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output logic io_axi_imem_bready,
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output logic [3:0] io_axi_imem_arid,
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output logic [31:0] io_axi_imem_araddr,
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output logic [7:0] io_axi_imem_arlen,
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output logic [2:0] io_axi_imem_arsize,
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output logic [1:0] io_axi_imem_arburst,
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output logic io_axi_imem_arlock,
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output logic [3:0] io_axi_imem_arcache,
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output logic [2:0] io_axi_imem_arprot,
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output logic [3:0] io_axi_imem_arregion,
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output logic [3:0] io_axi_imem_aruser,
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output logic [3:0] io_axi_imem_arqos,
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output logic io_axi_imem_arvalid,
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input logic io_axi_imem_arready,
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input logic [3:0] io_axi_imem_rid,
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input logic [31:0] io_axi_imem_rdata,
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input logic [1:0] io_axi_imem_rresp,
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input logic io_axi_imem_rlast,
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input logic [3:0] io_axi_imem_ruser,
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input logic io_axi_imem_rvalid,
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output logic io_axi_imem_rready,
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// Data Memory Interface
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output logic [3:0] io_axi_dmem_awid,
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output logic [31:0] io_axi_dmem_awaddr,
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output logic [7:0] io_axi_dmem_awlen,
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output logic [2:0] io_axi_dmem_awsize,
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output logic [1:0] io_axi_dmem_awburst,
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output logic io_axi_dmem_awlock,
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output logic [3:0] io_axi_dmem_awcache,
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output logic [2:0] io_axi_dmem_awprot,
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output logic [3:0] io_axi_dmem_awregion,
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output logic [3:0] io_axi_dmem_awuser,
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output logic [3:0] io_axi_dmem_awqos,
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output logic io_axi_dmem_awvalid,
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input logic io_axi_dmem_awready,
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output logic [31:0] io_axi_dmem_wdata,
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output logic [3:0] io_axi_dmem_wstrb,
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output logic io_axi_dmem_wlast,
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output logic [3:0] io_axi_dmem_wuser,
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output logic io_axi_dmem_wvalid,
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input logic io_axi_dmem_wready,
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input logic [3:0] io_axi_dmem_bid,
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input logic [1:0] io_axi_dmem_bresp,
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input logic io_axi_dmem_bvalid,
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input logic [3:0] io_axi_dmem_buser,
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output logic io_axi_dmem_bready,
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output logic [3:0] io_axi_dmem_arid,
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output logic [31:0] io_axi_dmem_araddr,
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output logic [7:0] io_axi_dmem_arlen,
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output logic [2:0] io_axi_dmem_arsize,
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output logic [1:0] io_axi_dmem_arburst,
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output logic io_axi_dmem_arlock,
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output logic [3:0] io_axi_dmem_arcache,
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output logic [2:0] io_axi_dmem_arprot,
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output logic [3:0] io_axi_dmem_arregion,
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output logic [3:0] io_axi_dmem_aruser,
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output logic [3:0] io_axi_dmem_arqos,
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output logic io_axi_dmem_arvalid,
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input logic io_axi_dmem_arready,
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input logic [3:0] io_axi_dmem_rid,
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input logic [31:0] io_axi_dmem_rdata,
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input logic [1:0] io_axi_dmem_rresp,
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input logic io_axi_dmem_rlast,
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input logic [3:0] io_axi_dmem_ruser,
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input logic io_axi_dmem_rvalid,
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output logic io_axi_dmem_rready
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);
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//-------------------------------------------------------------------------------
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// Local parameters
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//-------------------------------------------------------------------------------
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localparam int unsigned SCR1_CLUSTER_TOP_RST_SYNC_STAGES_NUM = 2;
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//-------------------------------------------------------------------------------
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// Local signal declaration
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//-------------------------------------------------------------------------------
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// Reset logic
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logic pwrup_rst_n_sync;
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logic rst_n_sync;
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logic cpu_rst_n_sync;
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logic core_rst_n_local;
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logic axi_rst_n;
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`ifdef SCR1_DBG_EN
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logic tapc_trst_n;
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`endif // SCR1_DBG_EN
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// Instruction memory interface from core to router
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logic core_imem_req_ack;
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logic core_imem_req;
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type_scr1_mem_cmd_e core_imem_cmd;
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logic [`SCR1_IMEM_AWIDTH-1:0] core_imem_addr;
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logic [`SCR1_IMEM_DWIDTH-1:0] core_imem_rdata;
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type_scr1_mem_resp_e core_imem_resp;
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// Data memory interface from core to router
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logic core_dmem_req_ack;
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logic core_dmem_req;
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type_scr1_mem_cmd_e core_dmem_cmd;
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type_scr1_mem_width_e core_dmem_width;
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logic [`SCR1_DMEM_AWIDTH-1:0] core_dmem_addr;
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logic [`SCR1_DMEM_DWIDTH-1:0] core_dmem_wdata;
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logic [`SCR1_DMEM_DWIDTH-1:0] core_dmem_rdata;
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type_scr1_mem_resp_e core_dmem_resp;
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// Instruction memory interface from router to AXI bridge
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logic axi_imem_req_ack;
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logic axi_imem_req;
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type_scr1_mem_cmd_e axi_imem_cmd;
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logic [`SCR1_IMEM_AWIDTH-1:0] axi_imem_addr;
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logic [`SCR1_IMEM_DWIDTH-1:0] axi_imem_rdata;
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type_scr1_mem_resp_e axi_imem_resp;
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// Data memory interface from router to AXI bridge
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logic axi_dmem_req_ack;
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logic axi_dmem_req;
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type_scr1_mem_cmd_e axi_dmem_cmd;
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type_scr1_mem_width_e axi_dmem_width;
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logic [`SCR1_DMEM_AWIDTH-1:0] axi_dmem_addr;
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logic [`SCR1_DMEM_DWIDTH-1:0] axi_dmem_wdata;
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logic [`SCR1_DMEM_DWIDTH-1:0] axi_dmem_rdata;
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type_scr1_mem_resp_e axi_dmem_resp;
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`ifdef SCR1_TCM_EN
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// Instruction memory interface from router to TCM
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logic tcm_imem_req_ack;
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logic tcm_imem_req;
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type_scr1_mem_cmd_e tcm_imem_cmd;
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logic [`SCR1_IMEM_AWIDTH-1:0] tcm_imem_addr;
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logic [`SCR1_IMEM_DWIDTH-1:0] tcm_imem_rdata;
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type_scr1_mem_resp_e tcm_imem_resp;
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// Data memory interface from router to TCM
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logic tcm_dmem_req_ack;
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logic tcm_dmem_req;
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type_scr1_mem_cmd_e tcm_dmem_cmd;
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type_scr1_mem_width_e tcm_dmem_width;
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logic [`SCR1_DMEM_AWIDTH-1:0] tcm_dmem_addr;
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logic [`SCR1_DMEM_DWIDTH-1:0] tcm_dmem_wdata;
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logic [`SCR1_DMEM_DWIDTH-1:0] tcm_dmem_rdata;
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type_scr1_mem_resp_e tcm_dmem_resp;
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`endif // SCR1_TCM_EN
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// Data memory interface from router to memory-mapped timer
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logic timer_dmem_req_ack;
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logic timer_dmem_req;
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type_scr1_mem_cmd_e timer_dmem_cmd;
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type_scr1_mem_width_e timer_dmem_width;
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logic [`SCR1_DMEM_AWIDTH-1:0] timer_dmem_addr;
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logic [`SCR1_DMEM_DWIDTH-1:0] timer_dmem_wdata;
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logic [`SCR1_DMEM_DWIDTH-1:0] timer_dmem_rdata;
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type_scr1_mem_resp_e timer_dmem_resp;
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// Misc
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logic timer_irq;
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logic [63:0] timer_val;
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logic axi_reinit;
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logic axi_imem_idle;
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logic axi_dmem_idle;
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//-------------------------------------------------------------------------------
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// Reset logic
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//-------------------------------------------------------------------------------
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// Power-Up Reset synchronizer
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scr1_reset_sync_cell #(
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.STAGES_AMOUNT (SCR1_CLUSTER_TOP_RST_SYNC_STAGES_NUM)
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) i_pwrup_rstn_reset_sync (
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.rst_n (pwrup_rst_n ),
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.clk (clk ),
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.test_rst_n (test_rst_n ),
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.test_mode (test_mode ),
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.rst_n_in (1'b1 ),
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.rst_n_out (pwrup_rst_n_sync)
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);
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// Regular Reset synchronizer
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scr1_reset_sync_cell #(
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.STAGES_AMOUNT (SCR1_CLUSTER_TOP_RST_SYNC_STAGES_NUM)
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) i_rstn_reset_sync (
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.rst_n (pwrup_rst_n ),
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.clk (clk ),
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.test_rst_n (test_rst_n ),
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.test_mode (test_mode ),
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.rst_n_in (rst_n ),
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.rst_n_out (rst_n_sync )
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);
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// CPU Reset synchronizer
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scr1_reset_sync_cell #(
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.STAGES_AMOUNT (SCR1_CLUSTER_TOP_RST_SYNC_STAGES_NUM)
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) i_cpu_rstn_reset_sync (
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.rst_n (pwrup_rst_n ),
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.clk (clk ),
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.test_rst_n (test_rst_n ),
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.test_mode (test_mode ),
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.rst_n_in (cpu_rst_n ),
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.rst_n_out (cpu_rst_n_sync )
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);
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`ifdef SCR1_DBG_EN
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// TAPC Reset
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scr1_reset_and2_cell i_tapc_rstn_and2_cell (
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.rst_n_in ({trst_n, pwrup_rst_n}),
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.test_rst_n (test_rst_n ),
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.test_mode (test_mode ),
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.rst_n_out (tapc_trst_n )
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);
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`endif // SCR1_DBG_EN
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`ifdef SCR1_DBG_EN
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assign axi_rst_n = sys_rst_n_o;
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`else // SCR1_DBG_EN
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assign axi_rst_n = rst_n_sync;
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`endif // SCR1_DBG_EN
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//-------------------------------------------------------------------------------
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// SCR1 core instance
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//-------------------------------------------------------------------------------
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scr1_core_top i_core_top (
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// Common
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.pwrup_rst_n (pwrup_rst_n_sync ),
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.rst_n (rst_n_sync ),
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.cpu_rst_n (cpu_rst_n_sync ),
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.test_mode (test_mode ),
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.test_rst_n (test_rst_n ),
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.clk (clk ),
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.core_rst_n_o (core_rst_n_local ),
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.core_rdc_qlfy_o ( ),
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`ifdef SCR1_DBG_EN
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.sys_rst_n_o (sys_rst_n_o ),
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.sys_rdc_qlfy_o (sys_rdc_qlfy_o ),
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`endif // SCR1_DBG_EN
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// Fuses
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.core_fuse_mhartid_i (fuse_mhartid ),
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`ifdef SCR1_DBG_EN
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.tapc_fuse_idcode_i (fuse_idcode ),
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`endif // SCR1_DBG_EN
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// IRQ
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`ifdef SCR1_IPIC_EN
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.core_irq_lines_i (irq_lines ),
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`else // SCR1_IPIC_EN
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.core_irq_ext_i (ext_irq ),
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`endif // SCR1_IPIC_EN
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.core_irq_soft_i (soft_irq ),
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.core_irq_mtimer_i (timer_irq ),
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// Memory-mapped external timer
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.core_mtimer_val_i (timer_val ),
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`ifdef SCR1_DBG_EN
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// Debug interface
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.tapc_trst_n (tapc_trst_n ),
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.tapc_tck (tck ),
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.tapc_tms (tms ),
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.tapc_tdi (tdi ),
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.tapc_tdo (tdo ),
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.tapc_tdo_en (tdo_en ),
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`endif // SCR1_DBG_EN
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// Instruction memory interface
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.imem2core_req_ack_i (core_imem_req_ack),
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.core2imem_req_o (core_imem_req ),
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.core2imem_cmd_o (core_imem_cmd ),
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.core2imem_addr_o (core_imem_addr ),
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.imem2core_rdata_i (core_imem_rdata ),
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.imem2core_resp_i (core_imem_resp ),
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// Data memory interface
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.dmem2core_req_ack_i (core_dmem_req_ack),
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.core2dmem_req_o (core_dmem_req ),
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.core2dmem_cmd_o (core_dmem_cmd ),
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.core2dmem_width_o (core_dmem_width ),
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.core2dmem_addr_o (core_dmem_addr ),
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.core2dmem_wdata_o (core_dmem_wdata ),
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.dmem2core_rdata_i (core_dmem_rdata ),
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.dmem2core_resp_i (core_dmem_resp )
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);
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`ifdef SCR1_TCM_EN
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//-------------------------------------------------------------------------------
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// TCM instance
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//-------------------------------------------------------------------------------
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scr1_tcm #(
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.SCR1_TCM_SIZE (`SCR1_DMEM_AWIDTH'(~SCR1_TCM_ADDR_MASK + 1'b1))
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) i_tcm (
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.clk (clk ),
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.rst_n (core_rst_n_local),
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// Instruction interface to TCM
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.imem_req_ack (tcm_imem_req_ack),
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.imem_req (tcm_imem_req ),
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.imem_addr (tcm_imem_addr ),
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.imem_rdata (tcm_imem_rdata ),
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.imem_resp (tcm_imem_resp ),
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// Data interface to TCM
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.dmem_req_ack (tcm_dmem_req_ack),
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.dmem_req (tcm_dmem_req ),
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.dmem_cmd (tcm_dmem_cmd ),
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.dmem_width (tcm_dmem_width ),
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.dmem_addr (tcm_dmem_addr ),
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.dmem_wdata (tcm_dmem_wdata ),
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.dmem_rdata (tcm_dmem_rdata ),
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.dmem_resp (tcm_dmem_resp )
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);
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`endif // SCR1_TCM_EN
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//-------------------------------------------------------------------------------
|
||||
// Memory-mapped timer instance
|
||||
//-------------------------------------------------------------------------------
|
||||
scr1_timer i_timer (
|
||||
// Common
|
||||
.rst_n (core_rst_n_local ),
|
||||
.clk (clk ),
|
||||
.rtc_clk (rtc_clk ),
|
||||
|
||||
// Memory interface
|
||||
.dmem_req (timer_dmem_req ),
|
||||
.dmem_cmd (timer_dmem_cmd ),
|
||||
.dmem_width (timer_dmem_width ),
|
||||
.dmem_addr (timer_dmem_addr ),
|
||||
.dmem_wdata (timer_dmem_wdata ),
|
||||
.dmem_req_ack (timer_dmem_req_ack),
|
||||
.dmem_rdata (timer_dmem_rdata ),
|
||||
.dmem_resp (timer_dmem_resp ),
|
||||
|
||||
// Timer interface
|
||||
.timer_val (timer_val ),
|
||||
.timer_irq (timer_irq )
|
||||
);
|
||||
|
||||
|
||||
`ifdef SCR1_IMEM_ROUTER_EN
|
||||
//-------------------------------------------------------------------------------
|
||||
// Instruction memory router
|
||||
//-------------------------------------------------------------------------------
|
||||
scr1_imem_router #(
|
||||
.SCR1_ADDR_MASK (SCR1_TCM_ADDR_MASK),
|
||||
.SCR1_ADDR_PATTERN (SCR1_TCM_ADDR_PATTERN)
|
||||
) i_imem_router (
|
||||
.rst_n (core_rst_n_local ),
|
||||
.clk (clk ),
|
||||
|
||||
// Interface to core
|
||||
.imem_req_ack (core_imem_req_ack),
|
||||
.imem_req (core_imem_req ),
|
||||
.imem_cmd (core_imem_cmd ),
|
||||
.imem_addr (core_imem_addr ),
|
||||
.imem_rdata (core_imem_rdata ),
|
||||
.imem_resp (core_imem_resp ),
|
||||
|
||||
// Interface to AXI bridge
|
||||
.port0_req_ack (axi_imem_req_ack ),
|
||||
.port0_req (axi_imem_req ),
|
||||
.port0_cmd (axi_imem_cmd ),
|
||||
.port0_addr (axi_imem_addr ),
|
||||
.port0_rdata (axi_imem_rdata ),
|
||||
.port0_resp (axi_imem_resp ),
|
||||
|
||||
// Interface to TCM
|
||||
.port1_req_ack (tcm_imem_req_ack ),
|
||||
.port1_req (tcm_imem_req ),
|
||||
.port1_cmd (tcm_imem_cmd ),
|
||||
.port1_addr (tcm_imem_addr ),
|
||||
.port1_rdata (tcm_imem_rdata ),
|
||||
.port1_resp (tcm_imem_resp )
|
||||
);
|
||||
|
||||
`else // SCR1_IMEM_ROUTER_EN
|
||||
|
||||
assign axi_imem_req = core_imem_req;
|
||||
assign axi_imem_cmd = core_imem_cmd;
|
||||
assign axi_imem_addr = core_imem_addr;
|
||||
assign core_imem_req_ack = axi_imem_req_ack;
|
||||
assign core_imem_resp = axi_imem_resp;
|
||||
assign core_imem_rdata = axi_imem_rdata;
|
||||
|
||||
`endif // SCR1_IMEM_ROUTER_EN
|
||||
|
||||
|
||||
//-------------------------------------------------------------------------------
|
||||
// Data memory router
|
||||
//-------------------------------------------------------------------------------
|
||||
scr1_dmem_router #(
|
||||
|
||||
`ifdef SCR1_TCM_EN
|
||||
.SCR1_PORT1_ADDR_MASK (SCR1_TCM_ADDR_MASK),
|
||||
.SCR1_PORT1_ADDR_PATTERN (SCR1_TCM_ADDR_PATTERN),
|
||||
`else // SCR1_TCM_EN
|
||||
.SCR1_PORT1_ADDR_MASK (32'h00000000),
|
||||
.SCR1_PORT1_ADDR_PATTERN (32'hFFFFFFFF),
|
||||
`endif // SCR1_TCM_EN
|
||||
|
||||
.SCR1_PORT2_ADDR_MASK (SCR1_TIMER_ADDR_MASK),
|
||||
.SCR1_PORT2_ADDR_PATTERN (SCR1_TIMER_ADDR_PATTERN)
|
||||
|
||||
) i_dmem_router (
|
||||
.rst_n (core_rst_n_local ),
|
||||
.clk (clk ),
|
||||
|
||||
// Interface to core
|
||||
.dmem_req_ack (core_dmem_req_ack ),
|
||||
.dmem_req (core_dmem_req ),
|
||||
.dmem_cmd (core_dmem_cmd ),
|
||||
.dmem_width (core_dmem_width ),
|
||||
.dmem_addr (core_dmem_addr ),
|
||||
.dmem_wdata (core_dmem_wdata ),
|
||||
.dmem_rdata (core_dmem_rdata ),
|
||||
.dmem_resp (core_dmem_resp ),
|
||||
|
||||
`ifdef SCR1_TCM_EN
|
||||
// Interface to TCM
|
||||
.port1_req_ack (tcm_dmem_req_ack ),
|
||||
.port1_req (tcm_dmem_req ),
|
||||
.port1_cmd (tcm_dmem_cmd ),
|
||||
.port1_width (tcm_dmem_width ),
|
||||
.port1_addr (tcm_dmem_addr ),
|
||||
.port1_wdata (tcm_dmem_wdata ),
|
||||
.port1_rdata (tcm_dmem_rdata ),
|
||||
.port1_resp (tcm_dmem_resp ),
|
||||
`else // SCR1_TCM_EN
|
||||
.port1_req_ack (1'b0 ),
|
||||
.port1_req ( ),
|
||||
.port1_cmd ( ),
|
||||
.port1_width ( ),
|
||||
.port1_addr ( ),
|
||||
.port1_wdata ( ),
|
||||
.port1_rdata ('0 ),
|
||||
.port1_resp (SCR1_MEM_RESP_RDY_ER),
|
||||
`endif // SCR1_TCM_EN
|
||||
|
||||
// Interface to memory-mapped timer
|
||||
.port2_req_ack (timer_dmem_req_ack ),
|
||||
.port2_req (timer_dmem_req ),
|
||||
.port2_cmd (timer_dmem_cmd ),
|
||||
.port2_width (timer_dmem_width ),
|
||||
.port2_addr (timer_dmem_addr ),
|
||||
.port2_wdata (timer_dmem_wdata ),
|
||||
.port2_rdata (timer_dmem_rdata ),
|
||||
.port2_resp (timer_dmem_resp ),
|
||||
|
||||
// Interface to AXI bridge
|
||||
.port0_req_ack (axi_dmem_req_ack ),
|
||||
.port0_req (axi_dmem_req ),
|
||||
.port0_cmd (axi_dmem_cmd ),
|
||||
.port0_width (axi_dmem_width ),
|
||||
.port0_addr (axi_dmem_addr ),
|
||||
.port0_wdata (axi_dmem_wdata ),
|
||||
.port0_rdata (axi_dmem_rdata ),
|
||||
.port0_resp (axi_dmem_resp )
|
||||
);
|
||||
|
||||
|
||||
//-------------------------------------------------------------------------------
|
||||
// Instruction memory AXI bridge
|
||||
//-------------------------------------------------------------------------------
|
||||
scr1_mem_axi #(
|
||||
`ifdef SCR1_IMEM_AXI_REQ_BP
|
||||
.SCR1_AXI_REQ_BP (1),
|
||||
`else // SCR1_IMEM_AXI_REQ_BP
|
||||
.SCR1_AXI_REQ_BP (0),
|
||||
`endif // SCR1_IMEM_AXI_REQ_BP
|
||||
`ifdef SCR1_IMEM_AXI_RESP_BP
|
||||
.SCR1_AXI_RESP_BP (1)
|
||||
`else // SCR1_IMEM_AXI_RESP_BP
|
||||
.SCR1_AXI_RESP_BP (0)
|
||||
`endif // SCR1_IMEM_AXI_RESP_BP
|
||||
) i_imem_axi (
|
||||
.clk (clk ),
|
||||
.rst_n (axi_rst_n ),
|
||||
.axi_reinit (axi_reinit ),
|
||||
|
||||
// Interface to core
|
||||
.core_idle (axi_imem_idle ),
|
||||
.core_req_ack (axi_imem_req_ack ),
|
||||
.core_req (axi_imem_req ),
|
||||
.core_cmd (axi_imem_cmd ),
|
||||
.core_width (SCR1_MEM_WIDTH_WORD ),
|
||||
.core_addr (axi_imem_addr ),
|
||||
.core_wdata ('0 ),
|
||||
.core_rdata (axi_imem_rdata ),
|
||||
.core_resp (axi_imem_resp ),
|
||||
|
||||
// AXI I/O
|
||||
.awid (io_axi_imem_awid ),
|
||||
.awaddr (io_axi_imem_awaddr ),
|
||||
.awlen (io_axi_imem_awlen ),
|
||||
.awsize (io_axi_imem_awsize ),
|
||||
.awburst (io_axi_imem_awburst ),
|
||||
.awlock (io_axi_imem_awlock ),
|
||||
.awcache (io_axi_imem_awcache ),
|
||||
.awprot (io_axi_imem_awprot ),
|
||||
.awregion (io_axi_imem_awregion ),
|
||||
.awuser (io_axi_imem_awuser ),
|
||||
.awqos (io_axi_imem_awqos ),
|
||||
.awvalid (io_axi_imem_awvalid ),
|
||||
.awready (io_axi_imem_awready ),
|
||||
.wdata (io_axi_imem_wdata ),
|
||||
.wstrb (io_axi_imem_wstrb ),
|
||||
.wlast (io_axi_imem_wlast ),
|
||||
.wuser (io_axi_imem_wuser ),
|
||||
.wvalid (io_axi_imem_wvalid ),
|
||||
.wready (io_axi_imem_wready ),
|
||||
.bid (io_axi_imem_bid ),
|
||||
.bresp (io_axi_imem_bresp ),
|
||||
.bvalid (io_axi_imem_bvalid ),
|
||||
.buser (io_axi_imem_buser ),
|
||||
.bready (io_axi_imem_bready ),
|
||||
.arid (io_axi_imem_arid ),
|
||||
.araddr (io_axi_imem_araddr ),
|
||||
.arlen (io_axi_imem_arlen ),
|
||||
.arsize (io_axi_imem_arsize ),
|
||||
.arburst (io_axi_imem_arburst ),
|
||||
.arlock (io_axi_imem_arlock ),
|
||||
.arcache (io_axi_imem_arcache ),
|
||||
.arprot (io_axi_imem_arprot ),
|
||||
.arregion (io_axi_imem_arregion ),
|
||||
.aruser (io_axi_imem_aruser ),
|
||||
.arqos (io_axi_imem_arqos ),
|
||||
.arvalid (io_axi_imem_arvalid ),
|
||||
.arready (io_axi_imem_arready ),
|
||||
.rid (io_axi_imem_rid ),
|
||||
.rdata (io_axi_imem_rdata ),
|
||||
.rresp (io_axi_imem_rresp ),
|
||||
.rlast (io_axi_imem_rlast ),
|
||||
.ruser (io_axi_imem_ruser ),
|
||||
.rvalid (io_axi_imem_rvalid ),
|
||||
.rready (io_axi_imem_rready )
|
||||
);
|
||||
|
||||
|
||||
//-------------------------------------------------------------------------------
|
||||
// Data memory AXI bridge
|
||||
//-------------------------------------------------------------------------------
|
||||
scr1_mem_axi #(
|
||||
`ifdef SCR1_DMEM_AXI_REQ_BP
|
||||
.SCR1_AXI_REQ_BP (1),
|
||||
`else // SCR1_DMEM_AXI_REQ_BP
|
||||
.SCR1_AXI_REQ_BP (0),
|
||||
`endif // SCR1_DMEM_AXI_REQ_BP
|
||||
`ifdef SCR1_DMEM_AXI_RESP_BP
|
||||
.SCR1_AXI_RESP_BP (1)
|
||||
`else // SCR1_DMEM_AXI_RESP_BP
|
||||
.SCR1_AXI_RESP_BP (0)
|
||||
`endif // SCR1_DMEM_AXI_RESP_BP
|
||||
) i_dmem_axi (
|
||||
.clk (clk ),
|
||||
.rst_n (axi_rst_n ),
|
||||
.axi_reinit (axi_reinit ),
|
||||
|
||||
// Interface to core
|
||||
.core_idle (axi_dmem_idle ),
|
||||
.core_req_ack (axi_dmem_req_ack ),
|
||||
.core_req (axi_dmem_req ),
|
||||
.core_cmd (axi_dmem_cmd ),
|
||||
.core_width (axi_dmem_width ),
|
||||
.core_addr (axi_dmem_addr ),
|
||||
.core_wdata (axi_dmem_wdata ),
|
||||
.core_rdata (axi_dmem_rdata ),
|
||||
.core_resp (axi_dmem_resp ),
|
||||
|
||||
// AXI I/O
|
||||
.awid (io_axi_dmem_awid ),
|
||||
.awaddr (io_axi_dmem_awaddr ),
|
||||
.awlen (io_axi_dmem_awlen ),
|
||||
.awsize (io_axi_dmem_awsize ),
|
||||
.awburst (io_axi_dmem_awburst ),
|
||||
.awlock (io_axi_dmem_awlock ),
|
||||
.awcache (io_axi_dmem_awcache ),
|
||||
.awprot (io_axi_dmem_awprot ),
|
||||
.awregion (io_axi_dmem_awregion ),
|
||||
.awuser (io_axi_dmem_awuser ),
|
||||
.awqos (io_axi_dmem_awqos ),
|
||||
.awvalid (io_axi_dmem_awvalid ),
|
||||
.awready (io_axi_dmem_awready ),
|
||||
.wdata (io_axi_dmem_wdata ),
|
||||
.wstrb (io_axi_dmem_wstrb ),
|
||||
.wlast (io_axi_dmem_wlast ),
|
||||
.wuser (io_axi_dmem_wuser ),
|
||||
.wvalid (io_axi_dmem_wvalid ),
|
||||
.wready (io_axi_dmem_wready ),
|
||||
.bid (io_axi_dmem_bid ),
|
||||
.bresp (io_axi_dmem_bresp ),
|
||||
.bvalid (io_axi_dmem_bvalid ),
|
||||
.buser (io_axi_dmem_buser ),
|
||||
.bready (io_axi_dmem_bready ),
|
||||
.arid (io_axi_dmem_arid ),
|
||||
.araddr (io_axi_dmem_araddr ),
|
||||
.arlen (io_axi_dmem_arlen ),
|
||||
.arsize (io_axi_dmem_arsize ),
|
||||
.arburst (io_axi_dmem_arburst ),
|
||||
.arlock (io_axi_dmem_arlock ),
|
||||
.arcache (io_axi_dmem_arcache ),
|
||||
.arprot (io_axi_dmem_arprot ),
|
||||
.arregion (io_axi_dmem_arregion ),
|
||||
.aruser (io_axi_dmem_aruser ),
|
||||
.arqos (io_axi_dmem_arqos ),
|
||||
.arvalid (io_axi_dmem_arvalid ),
|
||||
.arready (io_axi_dmem_arready ),
|
||||
.rid (io_axi_dmem_rid ),
|
||||
.rdata (io_axi_dmem_rdata ),
|
||||
.rresp (io_axi_dmem_rresp ),
|
||||
.rlast (io_axi_dmem_rlast ),
|
||||
.ruser (io_axi_dmem_ruser ),
|
||||
.rvalid (io_axi_dmem_rvalid ),
|
||||
.rready (io_axi_dmem_rready )
|
||||
);
|
||||
|
||||
//-------------------------------------------------------------------------------
|
||||
// AXI reinit logic
|
||||
//-------------------------------------------------------------------------------
|
||||
always_ff @(negedge core_rst_n_local, posedge clk) begin
|
||||
if (~core_rst_n_local) axi_reinit <= 1'b1;
|
||||
else if (axi_imem_idle & axi_dmem_idle) axi_reinit <= 1'b0;
|
||||
end
|
||||
|
||||
endmodule : scr1_top_axi
|
||||
Reference in New Issue
Block a user