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Mikhail Yenuchenko
278
src_ref/top/scr1_dmem_router.sv
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278
src_ref/top/scr1_dmem_router.sv
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/// Copyright by Syntacore LLC © 2016-2021. See LICENSE for details
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/// @file <scr1_dmem_router.sv>
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/// @brief Data memory router
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///
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`include "scr1_memif.svh"
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`include "scr1_arch_description.svh"
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module scr1_dmem_router
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#(
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parameter SCR1_PORT1_ADDR_MASK = `SCR1_DMEM_AWIDTH'hFFFF0000,
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parameter SCR1_PORT1_ADDR_PATTERN = `SCR1_DMEM_AWIDTH'h00010000,
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parameter SCR1_PORT2_ADDR_MASK = `SCR1_DMEM_AWIDTH'hFFFF0000,
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parameter SCR1_PORT2_ADDR_PATTERN = `SCR1_DMEM_AWIDTH'h00020000
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)
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(
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// Control signals
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input logic rst_n,
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input logic clk,
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// Core interface
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output logic dmem_req_ack,
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input logic dmem_req,
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input type_scr1_mem_cmd_e dmem_cmd,
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input type_scr1_mem_width_e dmem_width,
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input logic [`SCR1_DMEM_AWIDTH-1:0] dmem_addr,
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input logic [`SCR1_DMEM_DWIDTH-1:0] dmem_wdata,
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output logic [`SCR1_DMEM_DWIDTH-1:0] dmem_rdata,
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output type_scr1_mem_resp_e dmem_resp,
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// PORT0 interface
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input logic port0_req_ack,
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output logic port0_req,
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output type_scr1_mem_cmd_e port0_cmd,
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output type_scr1_mem_width_e port0_width,
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output logic [`SCR1_DMEM_AWIDTH-1:0] port0_addr,
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output logic [`SCR1_DMEM_DWIDTH-1:0] port0_wdata,
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input logic [`SCR1_DMEM_DWIDTH-1:0] port0_rdata,
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input type_scr1_mem_resp_e port0_resp,
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// PORT1 interface
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input logic port1_req_ack,
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output logic port1_req,
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output type_scr1_mem_cmd_e port1_cmd,
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output type_scr1_mem_width_e port1_width,
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output logic [`SCR1_DMEM_AWIDTH-1:0] port1_addr,
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output logic [`SCR1_DMEM_DWIDTH-1:0] port1_wdata,
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input logic [`SCR1_DMEM_DWIDTH-1:0] port1_rdata,
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input type_scr1_mem_resp_e port1_resp,
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// PORT2 interface
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input logic port2_req_ack,
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output logic port2_req,
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output type_scr1_mem_cmd_e port2_cmd,
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output type_scr1_mem_width_e port2_width,
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output logic [`SCR1_DMEM_AWIDTH-1:0] port2_addr,
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output logic [`SCR1_DMEM_DWIDTH-1:0] port2_wdata,
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input logic [`SCR1_DMEM_DWIDTH-1:0] port2_rdata,
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input type_scr1_mem_resp_e port2_resp
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);
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//-------------------------------------------------------------------------------
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// Local types declaration
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//-------------------------------------------------------------------------------
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typedef enum logic {
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SCR1_FSM_ADDR,
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SCR1_FSM_DATA
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} type_scr1_fsm_e;
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typedef enum logic [1:0] {
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SCR1_SEL_PORT0,
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SCR1_SEL_PORT1,
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SCR1_SEL_PORT2
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} type_scr1_sel_e;
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//-------------------------------------------------------------------------------
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// Local signal declaration
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//-------------------------------------------------------------------------------
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type_scr1_fsm_e fsm;
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type_scr1_sel_e port_sel;
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type_scr1_sel_e port_sel_r;
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logic [`SCR1_DMEM_DWIDTH-1:0] sel_rdata;
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type_scr1_mem_resp_e sel_resp;
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logic sel_req_ack;
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//-------------------------------------------------------------------------------
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// FSM
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//-------------------------------------------------------------------------------
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always_comb begin
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port_sel = SCR1_SEL_PORT0;
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if ((dmem_addr & SCR1_PORT1_ADDR_MASK) == SCR1_PORT1_ADDR_PATTERN) begin
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port_sel = SCR1_SEL_PORT1;
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end else if ((dmem_addr & SCR1_PORT2_ADDR_MASK) == SCR1_PORT2_ADDR_PATTERN) begin
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port_sel = SCR1_SEL_PORT2;
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end
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end
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always_ff @(negedge rst_n, posedge clk) begin
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if (~rst_n) begin
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fsm <= SCR1_FSM_ADDR;
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port_sel_r <= SCR1_SEL_PORT0;
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end else begin
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case (fsm)
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SCR1_FSM_ADDR : begin
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if (dmem_req & sel_req_ack) begin
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fsm <= SCR1_FSM_DATA;
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port_sel_r <= port_sel;
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end
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end
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SCR1_FSM_DATA : begin
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case (sel_resp)
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SCR1_MEM_RESP_RDY_OK : begin
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if (dmem_req & sel_req_ack) begin
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fsm <= SCR1_FSM_DATA;
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port_sel_r <= port_sel;
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end else begin
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fsm <= SCR1_FSM_ADDR;
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end
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end
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SCR1_MEM_RESP_RDY_ER : begin
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fsm <= SCR1_FSM_ADDR;
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end
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default : begin
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end
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endcase
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end
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default : begin
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end
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endcase
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end
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end
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always_comb begin
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if ((fsm == SCR1_FSM_ADDR) | ((fsm == SCR1_FSM_DATA) & (sel_resp == SCR1_MEM_RESP_RDY_OK))) begin
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case (port_sel)
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SCR1_SEL_PORT0 : sel_req_ack = port0_req_ack;
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SCR1_SEL_PORT1 : sel_req_ack = port1_req_ack;
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SCR1_SEL_PORT2 : sel_req_ack = port2_req_ack;
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default : sel_req_ack = 1'b0;
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endcase
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end else begin
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sel_req_ack = 1'b0;
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end
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end
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always_comb begin
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case (port_sel_r)
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SCR1_SEL_PORT0 : begin
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sel_rdata = port0_rdata;
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sel_resp = port0_resp;
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end
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SCR1_SEL_PORT1 : begin
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sel_rdata = port1_rdata;
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sel_resp = port1_resp;
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end
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SCR1_SEL_PORT2 : begin
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sel_rdata = port2_rdata;
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sel_resp = port2_resp;
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end
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default : begin
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sel_rdata = '0;
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sel_resp = SCR1_MEM_RESP_RDY_ER;
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end
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endcase
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end
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//-------------------------------------------------------------------------------
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// Interface to core
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//-------------------------------------------------------------------------------
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assign dmem_req_ack = sel_req_ack;
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assign dmem_rdata = sel_rdata;
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assign dmem_resp = sel_resp;
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//-------------------------------------------------------------------------------
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// Interface to PORT0
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//-------------------------------------------------------------------------------
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always_comb begin
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port0_req = 1'b0;
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case (fsm)
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SCR1_FSM_ADDR : begin
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port0_req = dmem_req & (port_sel == SCR1_SEL_PORT0);
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end
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SCR1_FSM_DATA : begin
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if (sel_resp == SCR1_MEM_RESP_RDY_OK) begin
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port0_req = dmem_req & (port_sel == SCR1_SEL_PORT0);
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end
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end
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default : begin
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end
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endcase
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end
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`ifdef SCR1_XPROP_EN
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assign port0_cmd = (port_sel == SCR1_SEL_PORT0) ? dmem_cmd : SCR1_MEM_CMD_ERROR;
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assign port0_width = (port_sel == SCR1_SEL_PORT0) ? dmem_width : SCR1_MEM_WIDTH_ERROR;
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assign port0_addr = (port_sel == SCR1_SEL_PORT0) ? dmem_addr : 'x;
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assign port0_wdata = (port_sel == SCR1_SEL_PORT0) ? dmem_wdata : 'x;
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`else // SCR1_XPROP_EN
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assign port0_cmd = dmem_cmd ;
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assign port0_width = dmem_width;
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assign port0_addr = dmem_addr ;
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assign port0_wdata = dmem_wdata;
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`endif // SCR1_XPROP_EN
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//-------------------------------------------------------------------------------
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// Interface to PORT1
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//-------------------------------------------------------------------------------
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always_comb begin
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port1_req = 1'b0;
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case (fsm)
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SCR1_FSM_ADDR : begin
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port1_req = dmem_req & (port_sel == SCR1_SEL_PORT1);
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end
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SCR1_FSM_DATA : begin
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if (sel_resp == SCR1_MEM_RESP_RDY_OK) begin
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port1_req = dmem_req & (port_sel == SCR1_SEL_PORT1);
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end
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end
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default : begin
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end
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endcase
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end
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`ifdef SCR1_XPROP_EN
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assign port1_cmd = (port_sel == SCR1_SEL_PORT1) ? dmem_cmd : SCR1_MEM_CMD_ERROR;
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assign port1_width = (port_sel == SCR1_SEL_PORT1) ? dmem_width : SCR1_MEM_WIDTH_ERROR;
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assign port1_addr = (port_sel == SCR1_SEL_PORT1) ? dmem_addr : 'x;
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assign port1_wdata = (port_sel == SCR1_SEL_PORT1) ? dmem_wdata : 'x;
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`else // SCR1_XPROP_EN
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assign port1_cmd = dmem_cmd ;
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assign port1_width = dmem_width;
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assign port1_addr = dmem_addr ;
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assign port1_wdata = dmem_wdata;
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`endif // SCR1_XPROP_EN
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//-------------------------------------------------------------------------------
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// Interface to PORT2
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//-------------------------------------------------------------------------------
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always_comb begin
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port2_req = 1'b0;
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case (fsm)
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SCR1_FSM_ADDR : begin
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port2_req = dmem_req & (port_sel == SCR1_SEL_PORT2);
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end
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SCR1_FSM_DATA : begin
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if (sel_resp == SCR1_MEM_RESP_RDY_OK) begin
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port2_req = dmem_req & (port_sel == SCR1_SEL_PORT2);
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end
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end
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default : begin
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end
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endcase
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end
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`ifdef SCR1_XPROP_EN
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assign port2_cmd = (port_sel == SCR1_SEL_PORT2) ? dmem_cmd : SCR1_MEM_CMD_ERROR;
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assign port2_width = (port_sel == SCR1_SEL_PORT2) ? dmem_width : SCR1_MEM_WIDTH_ERROR;
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assign port2_addr = (port_sel == SCR1_SEL_PORT2) ? dmem_addr : 'x;
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assign port2_wdata = (port_sel == SCR1_SEL_PORT2) ? dmem_wdata : 'x;
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`else // SCR1_XPROP_EN
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assign port2_cmd = dmem_cmd ;
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assign port2_width = dmem_width;
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assign port2_addr = dmem_addr ;
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assign port2_wdata = dmem_wdata;
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`endif // SCR1_XPROP_EN
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`ifdef SCR1_TRGT_SIMULATION
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//-------------------------------------------------------------------------------
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// Assertion
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//-------------------------------------------------------------------------------
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SCR1_SVA_DMEM_RT_XCHECK : assert property (
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@(negedge clk) disable iff (~rst_n)
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dmem_req |-> !$isunknown({port_sel, dmem_cmd, dmem_width})
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) else $error("DMEM router Error: unknown values");
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`endif // SCR1_TRGT_SIMULATION
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endmodule : scr1_dmem_router
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