From 099605414c0e9e08811eb1197063b9a88d65e4ad Mon Sep 17 00:00:00 2001
From: Mikhail Yenuchenko <76039929+mixeme@users.noreply.github.com>
Date: Wed, 21 Jan 2026 14:05:16 +0300
Subject: [PATCH] Move file

---
 src/rtl/filelist.v     | 63 ++++++++++++++++++++++++++++++++++++++++++
 src_ref/rtl/filelist.v | 63 ------------------------------------------
 2 files changed, 63 insertions(+), 63 deletions(-)
 create mode 100644 src/rtl/filelist.v
 delete mode 100644 src_ref/rtl/filelist.v

diff --git a/src/rtl/filelist.v b/src/rtl/filelist.v
new file mode 100644
index 0000000..4aabc63
--- /dev/null
+++ b/src/rtl/filelist.v
@@ -0,0 +1,63 @@
+// `include "../scr1_custom_define.svh"
+// `include "../scr1_arch_custom.svh"
+
+// includes
+// /home/yenuchenko/riscv_school/scr1/scr1-master/src/includes
+`include "scr1/scr1_ahb.svh"
+`include "scr1/scr1_arch_description.svh"
+`include "scr1/scr1_arch_types.svh"
+`include "scr1/scr1_csr.svh"
+`include "scr1/scr1_dm.svh"
+`include "scr1/scr1_hdu.svh"
+`include "scr1/scr1_ipic.svh"
+`include "scr1/scr1_memif.svh"
+`include "scr1/scr1_riscv_isa_decoding.svh"
+`include "scr1/scr1_scu.svh"
+`include "scr1/scr1_search_ms1.svh"
+`include "scr1/scr1_tapc.svh"
+`include "scr1/scr1_tdu.svh"
+
+// core
+// /home/yenuchenko/riscv_school/scr1/scr1-master/src/core
+`include "scr1/scr1_clk_ctrl.sv"
+`include "scr1/scr1_core_top.sv"
+`include "scr1/scr1_dm.sv"
+`include "scr1/scr1_dmi.sv"
+`include "scr1/scr1_scu.sv"
+`include "scr1/scr1_tapc.sv"
+`include "scr1/scr1_tapc_shift_reg.sv"
+`include "scr1/scr1_tapc_synchronizer.sv"
+
+// pipeline
+// /home/yenuchenko/riscv_school/scr1/scr1-master/src/core
+`include "scr1/scr1_ipic.sv"
+`include "scr1/scr1_pipe_csr.sv"
+`include "scr1/scr1_pipe_exu.sv"
+`include "scr1/scr1_pipe_hdu.sv"
+`include "scr1/scr1_pipe_ialu.sv"
+`include "scr1/scr1_pipe_idu.sv"
+`include "scr1/scr1_pipe_ifu.sv"
+`include "scr1/scr1_pipe_lsu.sv"
+`include "scr1/scr1_pipe_mprf.sv"
+`include "scr1/scr1_pipe_tdu.sv"
+`include "scr1/scr1_pipe_top.sv"
+`include "scr1/scr1_tracelog.sv"
+
+// primitives
+// /home/yenuchenko/riscv_school/scr1/scr1-master/src/core
+`include "scr1/scr1_cg.sv"
+`include "scr1/scr1_reset_cells.sv"
+
+// top
+// /home/yenuchenko/riscv_school/scr1/scr1-master/src/top
+`include "scr1/scr1_dmem_ahb.sv"
+`include "scr1/scr1_dmem_router.sv"
+`include "scr1/scr1_dp_memory.sv"
+`include "scr1/scr1_imem_ahb.sv"
+`include "scr1/scr1_imem_router.sv"
+`include "scr1/scr1_mem_axi.sv"
+`include "scr1/scr1_tcm.sv"
+`include "scr1/scr1_timer.sv"
+`include "scr1/scr1_top_ahb.sv"
+`include "scr1/scr1_top_axi.sv"
+
diff --git a/src_ref/rtl/filelist.v b/src_ref/rtl/filelist.v
deleted file mode 100644
index 70a883a..0000000
--- a/src_ref/rtl/filelist.v
+++ /dev/null
@@ -1,63 +0,0 @@
-// `include "../scr1_custom_define.svh"
-// `include "../scr1_arch_custom.svh"
-
-// includes
-// /home/yenuchenko/riscv_school/scr1/scr1-master/src/includes
-`include "../includes/scr1_ahb.svh"
-`include "../includes/scr1_arch_description.svh"
-`include "../includes/scr1_arch_types.svh"
-`include "../includes/scr1_csr.svh"
-`include "../includes/scr1_dm.svh"
-`include "../includes/scr1_hdu.svh"
-`include "../includes/scr1_ipic.svh"
-`include "../includes/scr1_memif.svh"
-`include "../includes/scr1_riscv_isa_decoding.svh"
-`include "../includes/scr1_scu.svh"
-`include "../includes/scr1_search_ms1.svh"
-`include "../includes/scr1_tapc.svh"
-`include "../includes/scr1_tdu.svh"
-
-// core
-// /home/yenuchenko/riscv_school/scr1/scr1-master/src/core
-`include "../core/scr1_clk_ctrl.sv"
-`include "../core/scr1_core_top.sv"
-`include "../core/scr1_dm.sv"
-`include "../core/scr1_dmi.sv"
-`include "../core/scr1_scu.sv"
-`include "../core/scr1_tapc.sv"
-`include "../core/scr1_tapc_shift_reg.sv"
-`include "../core/scr1_tapc_synchronizer.sv"
-
-// pipeline
-// /home/yenuchenko/riscv_school/scr1/scr1-master/src/core/pipeline
-`include "../core/pipeline/scr1_ipic.sv"
-`include "../core/pipeline/scr1_pipe_csr.sv"
-`include "../core/pipeline/scr1_pipe_exu.sv"
-`include "../core/pipeline/scr1_pipe_hdu.sv"
-`include "../core/pipeline/scr1_pipe_ialu.sv"
-`include "../core/pipeline/scr1_pipe_idu.sv"
-`include "../core/pipeline/scr1_pipe_ifu.sv"
-`include "../core/pipeline/scr1_pipe_lsu.sv"
-`include "../core/pipeline/scr1_pipe_mprf.sv"
-`include "../core/pipeline/scr1_pipe_tdu.sv"
-`include "../core/pipeline/scr1_pipe_top.sv"
-`include "../core/pipeline/scr1_tracelog.sv"
-
-// primitives
-// /home/yenuchenko/riscv_school/scr1/scr1-master/src/core/primitives
-`include "../core/primitives/scr1_cg.sv"
-`include "../core/primitives/scr1_reset_cells.sv"
-
-// top
-// /home/yenuchenko/riscv_school/scr1/scr1-master/src/top
-`include "../top/scr1_dmem_ahb.sv"
-`include "../top/scr1_dmem_router.sv"
-`include "../top/scr1_dp_memory.sv"
-`include "../top/scr1_imem_ahb.sv"
-`include "../top/scr1_imem_router.sv"
-`include "../top/scr1_mem_axi.sv"
-`include "../top/scr1_tcm.sv"
-`include "../top/scr1_timer.sv"
-`include "../top/scr1_top_ahb.sv"
-`include "../top/scr1_top_axi.sv"
-