riscv_school/riscv_school_pwm
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Mikhail Yenuchenko
2026-01-20 15:14:44 +03:00
parent 447fec03c7
commit fb0ac8dec1
1 changed files with 1 additions and 0 deletions
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scripts/scripts_syn/RUN_SYN.tcl
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@@ -29,6 +29,7 @@ set SYN_RESULTS_FOLDER "../results/results_syn"; # Results folde
### ============== PROC to run synthesis ============ ### ============== PROC to run synthesis ============
### Set TRUE to enable technological mapping and results export; otherwise only elaboration is active ### Set TRUE to enable technological mapping and results export; otherwise only elaboration is active
set MAPPING "FALSE"; set MAPPING "FALSE";
#set MAPPING "TRUE";
### ========== end of PROC to run synthesis ========= ### ========== end of PROC to run synthesis =========