riscv_school/riscv_school_pwm
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Update RUN_SYN.tcl

Browse Source
This commit is contained in:
ivanpiatak
2024-07-15 18:06:26 +03:00
committed by GitHub
parent 7b0bf7a03e
commit cdda88704e
1 changed files with 21 additions and 15 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
scripts/scripts_syn/RUN_SYN.tcl
View File

@@ -26,6 +26,11 @@ set SYN_REPORTS_FOLDER "../reports/reports_syn"; # Reports folde
set SYN_RESULTS_FOLDER "../results/results_syn"; # Results folder set SYN_RESULTS_FOLDER "../results/results_syn"; # Results folder
### ================= END of USER SETTINGS ========== ### ================= END of USER SETTINGS ==========
### ============== PROC to run synthesis ============
### Set TRUE to enable technological mapping; otherwise only elaboration is active
set MAPPING "FALSE";
### ========== end of PROC to run synthesis =========
### ================= SYNTHESIS ================= ### ================= SYNTHESIS =================
@@ -35,9 +40,10 @@ include ${SYN_CORNER}
# Read in Verilog HDL filelist for synthesis # Read in Verilog HDL filelist for synthesis
read_hdl -v2001 ${RTL_PATH}/${RTL_FILELIST_NAME} read_hdl -v2001 ${RTL_PATH}/${RTL_FILELIST_NAME}
# Synthesize (elabirate, no mapping) # Synthesize (elaborate, no mapping)
elaborate ${RTL_TOP_NAME} elaborate ${RTL_TOP_NAME}
if {$MAPPING eq "TRUE"} {
# Rear SDC constraints # Rear SDC constraints
read_sdc ${SYN_SDC_PATH}/${SYN_SDC_TOP_NAME} read_sdc ${SYN_SDC_PATH}/${SYN_SDC_TOP_NAME}
@@ -55,9 +61,9 @@ write_hdl -mapped > ${SYN_RESULTS_FOLDER}/${RTL_TOP_NAME}_syn_netlist.v
# Export SDC file for the next PaR stages # Export SDC file for the next PaR stages
write_sdc > ${SYN_RESULTS_FOLDER}/${RTL_TOP_NAME}_syn.sdc write_sdc > ${SYN_RESULTS_FOLDER}/${RTL_TOP_NAME}_syn.sdc
}
# Open RTL Compiler GUI # Open RTL Compiler GUI
gui_show gui_show
### ================= END of SYNTHESIS ========== ### ================= END of SYNTHESIS ==========