riscv_school/riscv_school_pwm
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[main] added 1.1 ver

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[main] added 1.1 ver
This commit is contained in:
ivanpiatak
2023-12-15 12:48:26 +03:00
committed by GitHub
parent 2d9f1cbc91
commit b5d53cac71
7 changed files with 244 additions and 10204 deletions
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22
scripts/scripts_syn/RUN_SYN.tcl
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@@ -6,24 +6,24 @@
### - set all USER settings;
### - create requred SDC file with the same name as your RTL top (e.g. RTL_TOP_MODULE.sdc)
### - open the terminal
### - cd to the main folder with the scripts, src, reports etc. (BE_ASIC_DESIGN_CADENCE_SCRIPTS folder)
### - run synthesis with RTL Compiler by typing in the same terminal "RTL_Compiler ./RUN_SYN.tcl"
### - cd to the main folder with the scripts, src, reports etc. (BE_ASIC_DESIGN_CADENCE_SCRIPTS folder) and then cd to the ./WORK_TMP_FOLDER
### - run synthesis with RTL Compiler by typing in the same terminal "RTL_Compiler ../scripts/scripts_syn/RUN_SYN.tcl"
### ================= USER SETTINGS =================
set RTL_TOP_NAME "PWM"; # RTL top module name
set RTL_PATH "./src/rtl"; # RTL path to the source files
set RTL_PATH "../src/rtl"; # RTL path to the source files
set RTL_FILELIST_NAME "filelist.v"; # RTL path to the filelist for synthesis
set RTL_FILELIST_NAME "filelist.v"; # RTL path to the filelist for synthesis
set SYN_SDC_TOP_NAME "${RTL_TOP_NAME}.sdc"; # SDC top file name
set SYN_SDC_PATH "./src/sdc"; # SDC path to the sources
set SYN_SDC_PATH "../src/sdc"; # SDC path to the sources
set SYN_CORNER "./scripts/scripts_aux/XFAB180_typ.tcl"; # Synthesis corner (typ by default)
set SYN_CORNER "../scripts/scripts_aux/XFAB180_typ.tcl"; # Synthesis corner (typ by default)
set SYN_REPORTS_FOLDER "./reports/reports_syn"; # Reports folder
set SYN_RESULTS_FOLDER "./results/results_syn"; # Results folder
set SYN_REPORTS_FOLDER "../reports/reports_syn"; # Reports folder
set SYN_RESULTS_FOLDER "../results/results_syn"; # Results folder
### ================= END of USER SETTINGS ==========
@@ -46,8 +46,9 @@ synthesize -to_mapped
synthesize -incremental
# Generate area and timing reports
report timing > ${SYN_REPORTS_FOLDER}/${RTL_TOP_NAME}_syn_timing_report.rpt
report area > ${SYN_REPORTS_FOLDER}/${RTL_TOP_NAME}_syn_area_report.rpt
report timing > ${SYN_REPORTS_FOLDER}/${RTL_TOP_NAME}_syn_timing_report.rpt
report area > ${SYN_REPORTS_FOLDER}/${RTL_TOP_NAME}_syn_area_report.rpt
report_timing -lint -verbose > ${SYN_REPORTS_FOLDER}/${RTL_TOP_NAME}_syn_timing_problems.rpt
# Export synthesized and mapped Verilog netlist - result of the synthesis
write_hdl -mapped > ${SYN_RESULTS_FOLDER}/${RTL_TOP_NAME}_syn_netlist.v
@@ -59,3 +60,4 @@ write_sdc > ${SYN_RESULTS_FOLDER}/${RTL_TOP_NAME}_syn.sdc
gui_show
### ================= END of SYNTHESIS ==========